Signal duration representation by conformational clock cycles in different time domains
AssigneeConexant Systems, Inc.
InventorsSergei Kessler, Asher Maimon
Life of this patent
Estimating the term…
Abstract
Circuitry and methodology for transferring a representation of a data signal between clock domains. In particular, the disclosure teaches a method for creating representations of signals input from a slow clock domain into a fast clock domain and vice versa. The methods and apparatus use a RAM-free architecture which may be easily incorporated into integrated circuits to enhance efficiency.
Claims7
A method for representing a data signal from a fast clock domain directly into a slow clock domain via a circuit, wherein said circuit detects the value of said signal at every clock cycle in said fast domain, and a plurality of said clock signal detection values is transmitted in parallel to at least two cycle number detection modules in said slow clock domain wherein each of said clock signal detection values is recorded as a high or a low, and wherein the total number of said detected high values or said detected low values is counted by a counter and output as a binary number by said counter, whereby said slow clock domain is informed of the number of cycles of said signal in said fast clock domain.
A circuit for transmitting a data signal from a slow clock domain to a fast clock domain, wherein an input signal comprising at least one slow clock cycle enters said circuit via a feedback flip-flop and is branched into two signal paths to LF companion AND gates, said LF companion AND gates being so connected in order to output complementary outputs, said feedback flip-flop causing a reversal in the states of said LF companion AND gates with the passage of each clock cycle, wherein said input signal entry and subsequent reversal of the states of said LF companion AND gates provides an indicator to said fast domain of the number of slow clock cycles comprising said input signal.
An integrated circuit including a circuit for transmitting a data signal from a slow clock domain to a fast clock domain, wherein an input signal comprising at least one slow clock cycle enters said circuit via a feedback flip-flop and is branched into two signal paths to LF companion AND gates, said LF companion AND gates being so connected in order to output complementary outputs, said feedback flip-flop causing a reversal in the states of said LF companion AND gates with the passage of each clock cycle, wherein said input signal entry and subsequent reversal of the states of said LF companion AND gates provides an indicator to said fast domain of the number of slow clock cycles comprising said input signal.
A chip incorporating a circuit for transmitting a data signal from a slow clock domain to a fast clock domain, wherein an input signal comprising at least one slow clock cycle enters said circuit via a feedback flip-flop and is branched into two signal paths to LF companion AND gates, said LF companion AND gates being so connected in order to output complementary outputs, said feedback flip-flop causing a reversal in the states of said LF companion AND gates with the passage of each clock cycle, wherein said input signal entry and subsequent reversal of the states of said LF companion AND gates provides an indicator to said fast domain of the number of slow clock cycles comprising said input signal.
A circuit for representing an input data signal from a fast clock domain directly into a slow clock domain, said circuit comprising a signal value detector for detecting the value of said signal at every clock cycle in said fast domain, said signal value detector being connected to at least two cycle number detection modules in said slow clock domain wherein each of said clock signal detection values is recorded as a high or a low, said cycle number detection modules being connected to a counter-converter for counting recorded signal detection values and for converting said clock signal detection values into a binary number, whereby said slow clock domain receives from said counter-converter a slow clock domain signal having the same number of cycles as said input signal in said fast clock domain.
Dependencies are inferred from the claim text.