Systems and methods for on-chip impedance termination

A method for providing impedance termination to first and second differential pins of an integrated circuit, the method comprising:

• providing a reference voltage at a first input of an amplifier by coupling a resistor divider to the first input of the amplifier, wherein providing the reference voltage further comprises coupling an off-chip resistor to third and fourth pins of the integrated circuit to complete the resistor divider,
• driving a feedback loop circuit coupled to an output of the amplifier so that a voltage at a second input of the amplifier matches the reference voltage;
• and
• driving an impedance matching circuit coupled between the first and the second differential pins using the amplifier.

An integrated circuit comprising:

• an amplifier circuit;
• a first transistor coupled between an output and a first input of the amplifier circuit;
• a resistor divider circuit coupled to a second input of the amplifier circuit;
• and
• a second transistor coupled between a pair of differntial pins and to the output of the amplifier circuit,
• wherein the drain-source resistance of the first transistor is substantially equal to the drain-source resistance of the second transistor.

An integrated circuit comprising:

• an amplifier circuit;
• a first transistor coupled between an output and a first input of the amplifier circuit, wherein the first transistor is coupled between first and second input/output pins of the integrated circuit;
• an impedance termination circuit comprising a second transistor coupled between third and fourth input/output pins of the integrated circuit and to the output of the amplifier circuit;
• a buffer circuit having input tenninak coupled to the third and the fourth pins;
• a first off p resistor coupled to the first pin of the integrated circuit;
• a second off-chip resistor coupled to the second pin of the integrated circuit;
• and
• a resistor divider coupled to a second input of the amplifier circuit.