Circuit configuration for the generation of a reference voltage

Abstract

The circuit configuration for the generation of a reference voltage (Vref) contains a reference voltage source (12) and a storage capacitor (C2) to which a voltage provided by a reference voltage source (12) can be applied via a controllable switch. The charging voltage of this storage capacitor (C1) is the reference voltage to be generated. The controllable switch (P1) is a MOS field-effect transistor with back gate (24) which, by means of a refresh signal supplied by a control circuit (22), can be put periodically into either a conducting or a non-conducting state. The back gate (24) of the MOS fieldeffect transistor (P1) is connected to an auxiliary storage capacitor (C2) to which the voltage supplied by the reference voltage source (12) can be applied via a further switch, consisting of a MOS field-effect transistor (P2) with back gate (26), and which is also controlled by the refresh signal. The back gate (26) of the further MOS field-effect transistor (P2) is connected to a fixed voltage, which is greater than the voltage supplied by the reference voltage source (12).

Dependencies are inferred from the claim text.