Vertical DRAM device with channel access transistor and stacked storage capacitor and associated method

Abstract

An integrated circuit memory device includes a substrate having at least one connection line therein and a plurality of memory cells formed on the substrate. Each memory cell includes a pillar comprising a lower source/drain region for a cell access transistor electrically connected to the connection line, an upper source/drain region for the cell access transistor, and at least one channel region extending vertically between the lower and upper source/drain regions. Each memory cell further includes at least one lower dielectric layer vertically adjacent the substrate and laterally adjacent the pillar and at least one upper dielectric layer vertically spaced above the at least one lower dielectric layer and laterally adjacent the pillar. Further, each memory cell includes at least one gate for the at least one channel of the cell access transistor between the lower and upper dielectric layers so that the vertical spacing therebetween defines a gate length for the cell access transistor. A storage capacitor is also included in each memory cell adjacent the upper source/drain region of the cell access transistor and is electrically connected thereto.

Dependencies are inferred from the claim text.