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US 6,603,164 B2Granted
Integrated semiconductor memory configuration
AssigneeInfineon Technologies AG
InventorsMarcus Kastner, Thomas Mikolajick
Life of this patent
Estimating the term…
Abstract
The integrated ferroelectric or DRAM semiconductor memory configuration has memory cells each with a selection transistor and a capacitor module that can be addressed by the selection transistor. The capacitors of successive memory cells are formed alternately on the front and rear sides of a substrate wafer.
Claims6
An integrated semiconductor memory configuration, comprising:
- a substrate having a front side and a rear side;
- a plurality of memory cells each having a selection transistor and a storage capacitor connected to and addressible by said selection transistor;
- said storage capacitors of respectively successive memory cells being formed alternately on said front side and said rear side of said substrate;
- and
- plugs formed on said rear side of said substrate, said plugs electrically connecting an electrode region of a respective said selection transistor with a capacitor plate, facing toward said selection transistor, of said storage capacitor disposed on said rear side of said substrate.
2 more elements
Dependencies are inferred from the claim text.