Semiconductor integrated circuit device including dummy patterns located to reduce dishing
AssigneesHitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
InventorsHiroyuki Uchiyama, Hiraku Chakihara, Teruhisa Ichise, Michimoto Kaminaga
Life of this patent
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Abstract
A large area dummy pattern DL is formed in a layer underneath a target T2 region formed in a scribe region SR of a wafer. A small area dummy pattern in a lower layer and a small area dummy pattern Ds2 in an upper layer are disposed in a region where the inter-pattern space of a pattern (active regions L1, L2, L3, gate electrode 17), which functions as an element of a product region PR and scribe region SR, is wide. The small area dummy pattern Ds2 in the upper layer is offset by ½ pitch relative to the small area dummy pattern Ds in the lower layer.
Claims2
A semiconductor integrated circuit device comprising a semiconductor substrate having a semiconductor element formed over a main surface of the semiconductor substrate, a first pattern formed on said main surface or any layer on said main surface, and a second pattern formed over an upper layer of said first pattern,
- said first pattern comprises a plurality of first dummy patterns, said second pattern comprises a plurality of second dummy patterns having a pattern pitch and pattern width of identical design dimensions as said first dummy patterns,
- said second dummy patterns are formed over inter-pattern spaces of said first dummy patterns in its flat surface position, and
- each second dummy pattern is isolated from each of the other second dummy patterns, wherein:
- said first pattern further comprises another dummy pattern having a larger area than that of said first dummy pattern, said second pattern further comprises a pattern used for optical recognition, and said pattern used for optical recognition is formed so that it is enclosed within the flat shape of said other dummy pattern.
Dependencies are inferred from the claim text.