Direct attachment semiconductor chip to organic substrate

#The present invention is related in general to the field of semiconductor devices and processes, and more specifically to methods for reliably assembling integrated circuit chips directly onto organic substrates.

#One of the major trends in semiconductor packaging is the effort to shrink the package outline so that the package consumes less area and less height when it is mounted onto the circuit board. Another powerful trend is the effort to achieve the outline reduction with minimum cost (both material and manufacturing cost). One of the most successful approaches has been the development of so-called “chip-scale packages”. These packages have an outline adding less than 20% to the chip area. A chip-scale package which has only the size of the chip itself, is often referred to as “chip-size package”.

#Within the semiconductor memory product families, one of the most promising concepts for chip-scale packages is the so-called “board-on-chip” design. Recently, several patent applications for this design concept have been submitted, entitled “Chip-Size Integrated Circuit Package” (Serial # 9702348-5 filed in Singapore on Jul. 2, 1997, and Serial # 08/994,627 filed in the U.S. on Dec. 19. 1997), “Thin Chip-Size Integrated Circuit Package and Method of Fabrication” (Serial # 9800005-2 and Serial # 9800006-0 filed in Singapore on Jan. 2, 1998), “Semiconductor Device Testing and Burn-in Methodology” (Serial # 9800617-4, filed in Singapore on Mar. 25, 1998, and Serial # 9800654-7, filed in Singapore on Mar. 28, 1998), “Method of Encapsulating Thin Semiconductor Chip-Scale Packages” (filed in Singapore on Aug. 25, 1998), all assigned to Texas Instruments Incorporated. Progress has been made in reducing the area and height requirements of packages, but frustrating problems still remain in maximizing adhesion, device reliability assurance and manufacturing cost reduction.

#FIG. 1 is a simplified and schematic cross section of a semiconductor chip directly attached to a substrate according to one embodiment of the present invention.

#FIG. 2 is a schematic enlarged cross section of a portion of the interface between the polyimide layer attached to the substrate.

#FIG. 3 is a simplified and schematic cross section of a semiconductor chip directly attached to a substrate, forming a chip-size package, according to another embodiment of the invention.

#The present invention is related to high frequency, high speed integrated circuit (IC) packages having both a low profile and a small outline. As defined herein, the term “outline” relates to the overall width and length of, for example, the entire IC package. The outline of the IC package is also referred to as the footprint of the IC package, because it defines the surface area on a motherboard that the IC package will occupy. Outline will be measured in, for example, square millimeters. As defined herein, the term “profile” refers to thickness or height of, for example, the IC package. The profile will be measured in, for example, millimeters. As defined herein, the term “substantially the same” refers to the relative outlines of the substrate and the semiconductor chip, which are within less than about 10% of one another. In embodiments where the chip and the substrate have the same outlines, the package is referred to as chip-size package. Importantly, the term substantially the same does not indicate which of the two components is larger, as either form is encompassed by the present invention.

#FIG. 1 is a simplified and schematic cross section of a semiconductor chip 10 attached to the second surface 11b of a substrate 11, forming a chip-scale package generally designated 100. Chip 10 has an active surface 10a comprising the integrated circuit and a plurality of bonding pads 10b, and a passive surface 10c. The semiconductor material may be silicon, silicon germanium, gallium arsenide, or any other semiconductor material used in electronic device production. In case of silicon ICs, the thickness of the chip is typically between 225 and 475 μm, and the chips may belong to product families such as dynamic random-access memories (DRAM), synchronous DRAM (SDRAM), static random-access memories (SRAM), erasable programmable read-only memories (EPROM), logic circuits (LOGIC), digital signal processors (DSP), application-specific ICs (ASIC), and many other integrated circuit components.

#All of these ICs receive in the wafer fabs a protective passivation overcoat (typically 0.5 to 1.0 μm thick) made of silicon nitride, which is impermeable against moisture penetration (not shown in FIGS. 1 to 4). It is of pivotal importance for the present invention that most of these ICs receive in the wafer fabs an additional layer of polyimide (typically 7 to 15 μm thick) on top of the silicon nitride, designated 12 in FIG. 1. The reason is threefold: The low dielectric constant of polyimide (relative to the dielectric constant of silicon nitride) lowers the capacitance of circuit elements and thus increases their speed; polyimide absorbs alpha radiation particles which are known to produce soft-errors in memory cells; and the organic nature of polyimide helps to mitigate thermomechanical stress in temperature excursions of the device. When these polyimide layers, and layers of related polymer chemistry, are preactivated, they acquire an adhesiveness such that an organic substrate can be directly attached to them.