Attenuator control circuit

An attenuator control circuit that applies a differential control input to the control signal inputs of a differential pair attenuator, comprising:

• first, second and third matched transistors coupled in a common emitter configuration;
• a current sink coupled to the common emitters of the first, second and third transistors;
• the second and third transistors forming a differential pair having first and second base terminals coupled to first and second base terminals, respectively, of the differential pair attenuator, the second and third transistors each having a collector terminal coupled to each other;
• a current mirror having a first current terminal coupled to a collector terminal of the first transistor and a second terminal coupled to the collector terminals of the second and third transistors;
• an amplifier having an input coupled to the current mirror and an output coupled to the base terminal of the third transistor;
• and
• a voltage source that applies a fixed bias voltage between the base terminals of the first and second transistors.

A temperature compensation circuit, comprising:

• first and second matched differential-to-single-ended stages, each including a current mirror and differential pair of transistors with common emitter terminals;
• a voltage source applying a reference voltage to a base terminal of a first of the differential pair of transistors of both of the first and second differential-to-single-ended stages;
• a temperature independent current sink coupled to the emitter terminals of the differential pair of transistors of the first differential-to-single-ended stage;
• a current sink, coupled to the emitter terminals of the differential pair of transistors of the second differential-to-single-ended stage, that sinks current proportional to temperature;
• an attenuator input gain control current source applied to a collector terminal of a second of the differential pair of transistors of the first differential-to-single-ended stage;
• an amplifier having an input coupled to the collector terminal of the second of the differential pair of transistors of the first differential-to-single-ended stage and an output coupled to a base terminal of a second of the differential pair of transistors of both of the first and second differential-to-single-ended stages;
• and
• an output circuit coupled to a collector terminal of a second of the differential pair of transistors of the second differential-to-single-ended stage that develops a fixed bias voltage based on a collector current of the second of the differential pair of transistors of the second differential-to-single-ended stage.