Silicon wafer
AssigneeShin-Etsu Handotai Co., Ltd.
InventorsMasahiro Kato, Masaro Tamatsuka, Osamu Imai, Akihiro Kimura, Tomosuke Yoshida
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AssigneeShin-Etsu Handotai Co., Ltd.
InventorsMasahiro Kato, Masaro Tamatsuka, Osamu Imai, Akihiro Kimura, Tomosuke Yoshida
Estimating the term…
The present invention provides a CZ silicon wafer, wherein the wafer includes rod-like void defects and/or plate-like void defects inside thereof, and a CZ silicon wafer, wherein the silicon wafer includes void defects inside the wafer, a maximum value of a ratio between long side length L1 and short side length L2 (L1/L2) in an optional rectangle circumscribed the void defect image projected on an optional {110} plane is 2.5 or more, and the silicon wafer including rod-like void defects and/or plate-like void defects inside the wafer, wherein a void defect density of the silicon wafer at a depth of from the wafer surface to at least 0.5 μm after the heat treatment is ½ or less than that of inside the wafer. According to this, the silicon wafer, which is suitable for expanding reducing effect of void defects by heat treatment up to a deeper region, can be obtained.
A silicon wafer produced by processing a silicon single crystal ingot grown by a Czochralski method, wherein the silicon wafer includes rod-like void defects and/or plate-like void defects inside the wafer and wherein a void defect density of the silicon wafer at a depth of from the wafer surface to at least 0.5 μm is ½ or less than that of the wafer inside.
A silicon wafer produced by processing a silicon single crystal ingot grown by a Czochralski method, wherein the silicon wafer includes void defects inside the wafer, wherein a maximum value of a ratio between long side length L1 and short side length L2 (L1/L2) of a rectangle projected to circumscribe the void defects in any {110} plane is 2.5 or more and wherein a void defect density of the silicon wafer at a depth of from the wafer surface to at least 0.5 μm is ½ or less than that of the wafer inside.
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