Method for improving integrated circuits bonding firmness
AssigneeIndustrial Technology Research Institute
InventorsJeng-Jie Peng, Ming-Dou Ker, Nien-Ming Wang
Life of this patent
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Abstract
A method for improving the integrated circuits bonding firmness, whose principle is that after the later film is piled on top of the previous film, the upper surface of the later film will be affected by the previous film. Among the metal layers of the multi-level interconnection, the metal layer under and most close to the bond pad metal (the top metal layer of the multi-level interconnection) has a regular or an irregular layout pattern, which is under the predetermined regions serving as bond pad windows. These regular or irregular layout patterns result in a rough upper surface, and then improves the firmness of bond wires.
Claims20
A method for improving the firmness of bond wires comprising the following steps:
- forming a composition layer to serve as a part of multi-level interconnection, said composition layer being composed of at least one conductive layer and at least one dielectric layer wherein said at least one conductive layer and said at least one dielectric layer are piled on top each other, a surface region of said conductive layer having a regular or an irregular layout pattern to increase the roughness of said composition layer;
- forming a bond pad conductive layer on said composition layer to serve as a bond pad region;
- forming a passivation layer on said bond pad conductive layer;
- forming a plurality of bond pad windows in said passivation layer to expose said bond pad conductive layer;
- and
- forming a plurality of bond wires in said bond pad windows to couple to an external circuit.
A method for improving the firmness of bond wires, the method comprising the steps of:
- forming an internal circuit on a substrate;
- forming an insulator layer on the internal circuit;
- forming a plurality of contact holes in said insulator layer;
- forming a plurality of plugs in said contact holes, and coupled with said internal circuit;
- forming a conductive layer having a regular or an irregular layout pattern formed thereon to increase the roughness of a upper surface of said conductive layer;
- forming a dielectric layer on said conductive layer for insulation;
- forming a bond pad conductive layer on said dielectric layer to serve as a bond pad region;
- forming a passivation layer on said bond pad conductive layer;
- forming a plurality of bond pad windows in said passivation layer to expose said bond pad conductive layer;
- and
- forming a plurality of bond wires in said bond pad windows to couple to an external circuit.
A method for improving the firmness of bond wires, the method comprising the steps of:
- (a) forming an internal circuit on a substrate;
- (b) forming an insulator layer on said internal circuit;
- (c) forming a plurality of contact holes in said insulator layer;
- (d) forming a plurality of plugs in said contact holes, and coupled with said internal circuit;
- (e) forming a conductive layer having a regular or an irregular layout pattern formed thereon to increase the roughness of a upper surface;
- (f) forming a dielectric layer on said conductive layer for insulation;
- (g) repeating the step (e) and the step (f) several times to form a composition layer, each film of said composition layer being piled on top of each other, to serve as a part of multi-level interconnection, and said composition layer is composed of at least one conductive layer and at least one dielectric layer, an upper surface of said conductive layer having a regular or an irregular layout pattern formed thereon to increase the roughness of said upper surface;
- (h) forming a bond pad conductive layer on said composition layer to serve as a bond pad region;
- (i) forming a passivation layer on said bond pad conductive layer;
- (j) forming a plurality of bond pad windows in said passivation layer to expose said bond pad conductive layer;
- and
- (k) forming a plurality of bond wires in said bond pad windows to couple to an external circuit.
A method for improving the firmness of bond wires, the method comprising the steps of:
- forming a composition layer on a substrate to serve as a part of multi-level interconnection, said composition layer being composed of at least one conductive layer and at least one dielectric layer wherein said at least one conductive layer and said at least one dielectric layer are piled on each other, a surface region of said conductive layer having a regular or an irregular layout pattern to increase the roughness of said conductive layer;
- forming a bond pad conductive layer on said composition layer to serve as a bond pad region;
- forming a plurality of bond pad windows in said bond pad conductive layer to expose said bond pad conductive layer;
- and
- forming a plurality of bond wires in said bond pad windows to couple to an external circuit for the firmness of bond wires.
Dependencies are inferred from the claim text.