US 6,596,599 B1Granted

Gate stack for high performance sub-micron CMOS devices

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorJyh-Chyurn Guo

Life of this patent

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Abstract

A new method is provided for the creation of sub-micron gate electrode structures. A high-k dielectric is used for the gate dielectric, providing increased inversion carrier density without having to resort to aggressive scaling of the thickness of the gate dielectric while at the same time preventing excessive gate leakage current from occurring. Further, air-gap spacers are formed over a stacked gate structure. The gate structure consists of pre-doped polysilicon of polysilicon-germanium, thus maintaining superior control over channel inversion carriers. The vertical field between the gate structure and the channel region of the gate is maximized by the high-k gate dielectric, capacitive coupling between the source/drain regions of the structure and the gate electrode is minimized by the gate spacers that contain an air gap.

Claims18

Dependent claims

A method for creating a gate electrode for high-performance sub-micron CMOS devices, comprising the steps of:

providing a silicon substrate having a bare surface;
depositing a layer of high-k gate dielectric over the surface of said substrate, followed by depositing a layer of bottom gate material over the surface of the layer of gate dielectric, followed by depositing a layer of top gate material over the surface of the layer of bottom gate material;
depositing a layer of hard mask material over the surface of the layer of top gate material followed by depositing a layer of bottom anti reflective coating material over the surface of the layer of hard mask material;
patterning the layer of bottom anti reflective coating material and the layer of hard mask material;
removing the patterned layer of bottom anti reflective coating material;
etching the layer of bottom gate material and the layer of top gate material in accordance with the patterned layer of hard mask material, creating an overhang of the layer of top gate material, exposing a surface area of said layer of high-k gate dielectric;
performing LDD implants into the surface of the substrate;
performing pocket and LDD implants under an angle with the surface of said substrate, said angle being different from a 90 degree angle by an amount;
removing the patterned layer of hard mask material from the surface of the patterned layer of top gate material;
creating first gate spacers over sidewalls of said patterned and etched bottom and top layers of gate material, said first gate spacers comprising a low-k dielectric material;
creating second gate spacers over the surface of said first gate spacers, said second gate spacers comprising TEOS or silicon nitride;
performing source/drain implants into the surface of the substrate, self-aligned with the second gate spacers;
creating salicided contact surface regions to the source and drain regions and the surface of the top layer of gate material;
and
removing said first gate spacers from between said patterned and etched layers of top and bottom gate material and said second spacers, said removing comprising:
(i) removing the second gate spacers from above the first gate spacers in upper regions of the first and second gate spacers by polishing the salicided surface of the top layer of gate material, applying methods of Chemical Mechanical Polishing (CMP) to this surface, exposing the first gate spacers;
(ii) creating a photoresist mask overlying the surface of said substrate and the surface of said second gate spacers, said photoresist mask exposing the first gate spacers;
and
(iii) applying an isotropic etch to the first gate spacers, thereby removing the first gate spacers.

16 more elements

A method for creating a gate electrode for high-performance sub-micron CMOS devices, comprising the steps of:

providing a silicon substrate;
performing a gate stack film deposition;
photo patterning and dry etching a hard mask;
performing a gate etch, using the created hard mask as an etch mask, creating a gate structure;
performing an Lightly Doped Diffusion (LDD) impurity implant into the surface of the substrate;
removing the hard mask from the surface of the gate structure;
coating a low-k film over the surface of the gate structure;
creating low-k gate spacers over sidewalls of the gate structure;
creating main gate spacers on the surface of the low-k spacers;
performing source/drain impurity implants into the surface of the substrate, self aligned with the gate structure;
saliciding source/drain surfaces and the surface of the gate structure;
and
removing said low-k gate spacers from between said gate structure and said main gate spacers, said removing comprising:
(i) creating openings in the main gate spacers by polishing the surface of the salicided surface of the gate structure, applying methods of Chemical Mechanical Polishing (CMP) to this surface, thereby exposing the low-k gate spacers;
(ii) creating a photoresist mask overlying the surface of said substrate and the surface of said main gate spacers, said photoresist mask exposing the openings created in the main gate spacers, thereby exposing the low-k gate spacers;
and
(iii) applying an isotropic etch to the low-k gate spacers, thereby removing the low-k gate spacers.

14 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/905,403Filed 16 Jul 2001
Granted: 22 Jul 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
H10D 64/01324
Characterised by the conductor: characterised by the sectional shape, e.g. T or inverted-T
H10D 64/671
Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes: the conductor having lateral variation…
H10D 64/679
Gate sidewall spacers: comprising air gaps