Method and apparatus for providing optimized access to circuits for debug, programming, and test

A method of accessing an electronic circuit, comprising the steps of:

• providing in parallel input data to at least one functional I/O of the electronic circuit by at least one data register, the data register being included in an access controller operatively coupled to the electronic circuit;
• receiving in parallel output data from the functional I/O of the electronic circuit by the data register;
• providing in parallel at least one address sequence to at least one address input of the electronic circuit by at least one address register, the address register being included in the access controller;
• and
• providing in parallel at least one functional control sequence to at least one control input of the electronic circuit by at least one control register of a protocol generator, the protocol generator being included in the access controller,
• wherein the first providing step, the receiving step, the second providing step, and the third providing step are performed substantially concurrently to enable testing, debugging, or programmable configuration of the electronic circuit.

A method of accessing an electronic circuit, comprising the steps of:

• programming a programmable logic device with a representation of an access controller, the access controller including
• a scan input terminal,
• a scan output terminal,
• a parallel access bus communicably coupleable to at least one functional I/O of the electronic circuit,
• an address bus communicably coupleable to at least one address input of the electronic circuit,
• a parallel control bus communicably coupleable to at least one control input of the electronic circuit,
• at least one data register having a serial input coupled to the scan input terminal for scanning input data into the data register, a plurality of data terminals coupled to the parallel access bus for providing in parallel the input data to the functional I/O and for receiving in parallel output data from the functional I/O of the electronic circuit, and a serial output coupled to the scan output terminal for scanning the output data out of the data register,
• at least one address register having a serial input coupled to the scan input terminal for scanning at least one address sequence into the address register, the address register being configured to provide in parallel the address sequence to the address input of the electronic circuit over the address bus, and
• a protocol generator coupled to the parallel control bus, the protocol generator including at least one control register for providing in parallel at least one functional control sequence to the control input of the electronic circuit over the parallel control bus;
• and
• operating the data register, the address register, and the protocol generator of the access controller substantially concurrently to enable testing, debugging, or programmable configuration of the electronic circuit.

A scan architecture, comprising:

• a scan controller including a state machine having a plurality of states, at least one of the plurality of states being programmable;
• and
• at least one scannable register coupled to the scan controller, the scannable register being configured to perform operational commands based at least in part on the plurality of states of the state machine,
• wherein at least one of the plurality of states is programmable to select between a shift-data state and a pause state.

A scan architecture, comprising:

• a scan controller including a state machine having a plurality of states, at least one of the plurality of states being programmable;
• and
• at least one scannable register coupled to the scan controller, the scannable register being configured to perform operational commands based at least in part on the plurality of states of the state machine,
• wherein at least one of the plurality of states is programmable to select between an update-data state and a capture-data state.

A scan architecture, comprising:

• a scan controller including a state machine having a plurality of states, at least one the plurality of states being programmable;
• and
• at least one scannable register coupled to the scan controller, the scannable register being configured to perform operational commands based at least in part on the plurality of states of the state machine,
• wherein the plurality of states comprises a variable sequence of programmable states.