US 6,594,681 B1 · Quotient digit selection logic for floating point division/square root

Abstract

Quotient digit selection logic using a three-bit carry propagate adder is presented. An enhanced quotient digit selection function prevents the working partial remainder from becoming negative if the result is exact. The enhanced quotient digit selection logic chooses a quotient digit of zero instead of a quotient digit of one when the actual partial remainder is zero. Using a four bit estimated partial remainder where the upper four bits are zero, a possible carry propagation into fourth most significant bit is detected. This can be accomplished by looking at the fourth most significant sum and carry bits of the redundant partial remainder. If they are both zero, then a carry propagation out of that bit position into the least significant position of the estimated partial remainder is not possible, and a quotient digit of zero is chosen. This provides a one cycle savings since negative partial remainders no longer need to be restored before calculating the sticky bit. Extra hardware is eliminated because it is no longer necessary to provide any extra mechanism for restoring the preliminary final partial remainder. Latency is improved because no additional cycle time is required to restore negative preliminary partial remainders. In an alternative embodiment, where the upper three bits of the estimated partial remainder are ones while the fourth most significant bit is zero, a quotient digit of negative one is chosen. This alternative embodiment allows correct exact results in all rounding modes including rounding toward plus or minus infinity.

Claims10

Dependent claims

A quotient digit selection circuit that determines a quotient digit in binary division and square root operations based upon a redundant partial remainder input, wherein the redundant partial remainder input includes first, second, third, and fourth sum bits and first, second, third, and fourth carry bits, and wherein the quotient digit chosen is output by asserting one of a minus output corresponding to a negative one quotient digit, a zero output corresponding to a zero quotient digit, and a plus output corresponding to a positive one quotient digit, the quotient digit selection circuit comprising:

a three-bit carry-propagate adder that takes the first, second, and third sum bits and the first, second, and third carry bits as inputs and produces first, second, and third estimated partial remainder bits as outputs;
a three-bit zero detector that takes the first, second, and third estimated partial remainder bits as inputs, and that produces an all-zero signal that is asserted if and only if the first, second, and third estimated partial remainder bits are all zeros;
a three-bit one detector that takes the first, second, and third estimated partial remainder bits as inputs, and produces an all-one signal that is asserted if and only if the first, second, and third estimated partial remainder bits are all ones;
a NOR gate that takes the fourth sum bit and the fourth carry bit as inputs and that produces a fourth bit zero signal;
and
a zero circuit that takes the all-one signal, the fourth bit zero signal, and the all-zero signal as inputs and that produces the zero output, such that the zero output is asserted if and only if either the all-one signal is asserted and the fourth bit zero signal is deasserted or the fourth bit zero signal and the all-zero signal are both asserted.

3 more elements

A method of providing a quotient digit selection circuit that determines a quotient digit in binary division and square root operations based upon a redundant partial remainder input, wherein the redundant partial remainder input includes first, second, third, and fourth sum bits and first, second, third, and fourth carry bits, and wherein the quotient digit chosen is output by asserting one of a minus output corresponding to a negative one quotient digit, a zero output corresponding to a zero-quotient digit, and a plus output corresponding to a positive one quotient digit, the method comprising:

providing a three-bit carry-propagate adder that takes the first, second, and third sum bits and the first, second, and third carry bits as inputs and produces first, second, and third estimated partial remainder bits as outputs;
providing a three-bit zero detector that takes the first, second, and third estimated partial remainder bits as inputs, and that produces an all-zero signal that is asserted if and only if the first, second, and third estimated partial remainder bits are all zeros;
providing a three-bit one detector that takes the first, second, and third estimated partial remainder bits as inputs, and that produces an all one signal that is asserted if and only if the first, second, and third estimated partial remainder bits are all ones;
providing a NOR gate that takes the fourth sum bit and the fourth carry bit as inputs and that produces a fourth bit zero signal;
and
providing a zero circuit that takes the all-one signal, the fourth bit zero signal, and the all-zero signal as inputs and that produces the zero output, such that the zero output is asserted if and only if either the all-one signal is asserted and the fourth bit zero signal is deasserted or the fourth bit zero signal and the all-zero signal are both asserted.

3 more elements

Dependencies are inferred from the claim text.

Quotient digit selection logic for floating point division/square root

Life of this patent

Quotient digit selection logic for floating point division/square root

Life of this patent

Abstract

Claims10