Buried channel strained silicon FET using a supply layer created through ion implantation
AssigneeAmberWave Systems Corporation
InventorEugene A. Fitzgerald
Life of this patent
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Abstract
A method of fabricating a buried channel FET including providing a relaxed SiGe layer on a substrate, providing a channel layer on the relaxed SiGe layer, providing a SiGe cap layer on the channel layer, and ion implanting a dopant supply. The dopant supply can be ion implanted in either the SiGe cap layer or the relaxed SiGe layer. In another embodiment, there is provided a method of fabricating a circuit including providing at least one strained channel, enhancement mode FET, and at least one strained channel, depletion mode FET on a substrate, and ion implanting a dopant supply in the depletion mode FET.
Claims43
A method of fabricating a buried channel FET, the method comprising the steps of:
- providing a relaxed SiGe layer on a substrate;
- providing a channel layer adjacent said relaxed SiGe layer;
- providing a SiGe cap layer adjacent said channel layer;
- and
- ion implanting a dopant supply in at least one of the relaxed SiGe layer and the SiGe cap layer so as to extend along said channel at least between source and drain regions thereof.
A method of fabricating a buried channel MOSFET, the method comprising the steps of:
- providing a relaxed SiGe layer on a substrate;
- providing a channel layer adjacent said relaxed SiGe layer;
- providing a SiGe cap layer adjacent said channel layer;
- providing a gate dielectric above said SiGe cap layer;
- and
- ion implanting a dopant supply in at least one of the SiGe cap layer and the relaxed SiGe layer so as to extend along said channel at least between source and drain regions thereof.
A method of fabricating a circuit comprising:
- providing at least one strained channel, enhancement mode FET and at least one strained channel, depletion mode FET on a substrate, the FETs each comprising a source and a drain;
- and
- ion implanting a dopant supply in said depletion mode FET, the dopant supply spanning said channel at least between said depletion mode FET source and said depletion mode FET drain.
A method of fabricating an inverter comprising:
- providing a strained buried channel depletion mode FET and a strained surface channel enhancement mode FET on a substrate, the FETs each comprising a source and a drain;
- and
- ion implanting a dopant supply in said strained buried channel depletion mode FET, the dopant supply spanning said channel at least between said depletion mode FET source and said depletion mode FET drain.
A method of fabricating an inverter comprising:
- providing a strained buried channel depletion mode MOSFET and a strained surface channel enhancement mode MOSFET on a substrate;
- and
- ion implanting a dopant supply in said strained buried channel depletion mode MOSFET.
Dependencies are inferred from the claim text.