Integrated memory and method for testing and repairing the integrated memory

An integrated memory, comprising:

• memory cells arranged in a memory cell block having a plurality of column lines and a plurality of row lines;
• said plurality of row lines including regular row lines and redundant row lines, and said plurality of column lines including regular column lines and redundant column lines;
• a self-test unit connected to said memory cell block and configured to:
• in an event of a read access to a current row line, check a correctness of the memory cell contents read and, upon detecting a defect, generate a defect signal for the current row line;
• in case of an ascertained defect, compare a calculated signature of the memory cell contents with a previously stored signature, for determining a respective column line in which the defect occurred;
• store the complete addresses of the memory cells in which a defect occurred successively in a shift register;
• if an address of a same memory cell is repeatedly stored in the shift register, determine the row line and column line associated with the memory cell;
• and
• when a predetermined repair condition is met, output a row repair signal for the associated row line or a column repair signal for the associated column line;
• a self-repair unit connected to said self-test unit and configured to:
• in response to a row repair signal, replace the current row line by a redundant row line during an operation of the integrated memory;
• and
• in response to a column repair signal, replace the column line that has been identified as defective by a redundant column line.

A method of testing and repairing an integrated memory having memory cells arranged in a memory cell block with a plurality of column lines and a plurality of row lines, and wherein the plurality of row lines includes regular row lines and redundant row lines, the method which comprises the following steps:

• reading memory cell contents of a current row line;
• checking a correctness of the memory cell contents read;
• generating a defect signal for the current row line in a defect case;
• detecting the defects ascertained for each regular row line;
• comparing a number of defects of the current row line with an average defect for the regular row lines;
• outputting a row repair signal for the current row line when a predetermined repair condition is met in the comparing step;
• and
• replacing the current row line by a redundant row line in response to a row repair signal during an operation of the integrated memory.

A method of testing and repairing an integrated memory having memory cells arranged in a memory cell block with a plurality of column lines and a plurality of row lines, the plurality of row lines including regular row lines and redundant row lines and the plurality of column lines including regular column lines and redundant column lines, the method which comprises the following steps:

• reading memory cell contents of a current row line;
• checking a correctness of the memory cell contents read;
• in a defect case, comparing a calculated signature of the memory cell contents with a previously stored signature for determining the column line in which the defect occurred;
• in a defect case, generating a defect signal for the current row line and a column line determined as defective;
• detecting the defects ascertained for each regular row line and each regular column line;
• comparing a number of defects of the current row line with an average defect for the regular row lines, and comparing a number of defects of a column line determined as defective with an average defect for the regular column lines;
• outputting a row repair signal for the current row line or a column repair signal for a column line identified as defective when a predetermined repair condition is met during the comparing steps;
• and
• replacing the current row line by a redundant row line in response to a row repair signal during an operation of the integrated memory, or replacing the column line identified as defective by a redundant column line in response to a column repair signal.

A method of testing and repairing an integrated memory having memory cells arranged in a memory cell block with a plurality of column lines and a plurality of row lines, the plurality of row lines including regular row lines and redundant row lines and the plurality of column lines including regular column lines and redundant column lines, the method which comprises the following steps:

• reading memory cell contents of a current row line;
• checking a correctness of the memory cell contents;
• in a defect case, comparing a calculated signature of the memory cell contents with a previously stored signature for determining the column line in which the defect occurred;
• in the defect case, generating a defect signal for the current row line and a column line determined as defective;
• storing the complete addresses of the memory cells in which a defect occurred;
• testing for repeated storage of the address of the same memory cell;
• upon reaching a predetermined number or frequency, determining the row line and column line associated with the memory cell;
• outputting a row repair signal for the associated row line or a column repair signal for the associated column line when a predetermined repair condition is met;
• and
• replacing the current row line by a redundant row line in response to a row repair signal during an operation of the integrated memory, or replacing the column line identified as defective by a redundant column line in response to a column repair signal.