Method for reading a structural phase-change memory
AssigneeIntel Corporation
InventorTyler A. Lowrey
Life of this patent
Estimating the term…
Abstract
A cell in a structural phase-change memory is programmed by raising cell voltage and cell current to programming threshold levels, and then lowering these to quiescent levels below their programming levels. A precharge pulse is then applied which raises the bitline voltage of the selected cell and does not raise the cell voltage and cell current to their programming levels. Then, the cell current is raised to a read level which is below the programming threshold level, and the bitline voltage is compared to a reference voltage while the cell current is at the read level.
Claims12
A method for operating a structural phase-change memory cell, comprising:
- programming a selected cell in a structural phase-change memory into a selected state by raising a cell voltage and a cell current for the selected cell to programming threshold levels, and then lowering the voltage and current to quiescent levels below their programming threshold levels;
- and then
- applying a precharge pulse which raises a bitline voltage of the selected cell and does not raise the cell voltage and cell current to their programming threshold levels;
- and then
- raising the cell current to a read level below the programming threshold level and comparing the bitline voltage, while the current is at the read level, to a reference voltage.
An integrated circuit comprising:
- a plurality of bitlines and a plurality of wordlines;
- a plurality of memory cells each of which has a volume of structural phase-change material coupled between a separate bitline-wordline pair of the plurality of bitlines and the plurality of wordlines to store information for that cell, the pair to be selected when reading that cell;
- and
- timing logic, pulse generation and drive circuitry coupled to the plurality of bitlines and the plurality of wordlines, to program a selected cell into a selected state by raising a cell voltage and cell current of the selected cell to programming threshold levels, and then lower the voltage and current to quiescent levels below their programming threshold levels, and then apply a precharge pulse to raise a bitline voltage of the selected cell and not raise the cell voltage and cell current to their programming threshold levels, and then raise said cell current to a read level below the programming threshold level and compare the bitline voltage obtained while said current is at the read level to a reference voltage.
An apparatus comprising:
- a portable electronic device having a printed circuit board on which a processor and a storage subsystem have been operatively installed, and a battery to power the printed circuit board, wherein the storage subsystem includes an integrated circuit having a plurality of bitlines and a plurality of wordlines, a plurality of memory cells each of which has a volume of structural phase-change material coupled between a separate bitline-wordline pair of the plurality of bitlines and the plurality of wordlines to store information for that cell, the pair to be selected when reading that cell, and timing logic, pulse generation and drive circuitry coupled to the plurality of bitlines and the plurality of wordlines, to program a selected cell into a selected state by raising a cell voltage and cell current of the selected cell to programming threshold levels, and then lower the voltage and current to quiescent levels below their programming threshold levels, and then apply a precharge pulse to raise a bitline voltage of the selected cell and not raise the cell voltage and cell current to their programming threshold levels, and then raise said cell current to a read level below the programming threshold level and compare the bitline voltage obtained while said current is at the read level to a reference voltage.
Dependencies are inferred from the claim text.