Inter-layer connection structure, multilayer printed circuit board and production processes therefor
AssigneeInternational Business Machines Corporation
InventorTakashi Katoh
Life of this patent
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Abstract
A process for forming a bump via to interconnect upper and lower circuits wherein a layer of metal is etched down, leaving a bump via and a lower portion of the layer. A lower circuit pattern is then formed in the lower portion, following which the pattern and bump via are covered with an insulating layer. Smoothing then results in the top surface of the bump via being exposed such that an upper circuit can then be formed on the insulating layer and in connection with said bump via.
Claims20
A process for producing an inter-layer connection structure for inter-layer connection between a lower electrical circuit and an upper electrical circuit, comprising the steps of:
- providing a core circuit board including a substrate and a metal layer positioned on one side of said substrate;
- applying a photoresist onto said metal layer of said core circuit board, and exposing and developing said photoresist to leave a photoresist pattern on a portion of said metal layer;
- etching said metal layer to a depth but not entirely through said metal layer to form at least one bump via from said metal layer having sides and an upper surface while leaving a lower portion of said metal layer on said side of said substrate;
- applying a photoresist onto said lower portion of said metal layer and onto said sides and upper surface of said at least one bump via to form a lower electrical circuit pattern in said lower portion, said forming of said lower electrical circuit pattern including removing said lower portion of said metal layer except for portions of said lower portion of said metal layer which form said electrical circuit pattern;
- forming an insulating layer on said lower electrical circuit and said at least one bump via;
- polishing said insulating layer to expose an upper surface of said at least one bump via;
- and
- forming an upper electrical circuit on said insulating layer in electrical contact with said at least one bump via.
A process for producing an inter-layer connection structure for inter-layer connection between a lower electrical circuit and an upper electrical circuit, comprising the steps of:
- providing a core circuit board including a substrate and a metal layer positioned on one side of said substrate;
- applying a photoresist onto said metal layer of said core circuit board, and exposing and developing said photoresist to leave a photoresist pattern on a portion of said metal layer;
- etching said metal layer to a depth but not entirely through said metal layer to form at least one bump via from said metal layer of a substantially truncated cone or trapezoidal shape having sides and an upper surface while leaving a portion of said metal layer on said side of said substrate;
- applying a photoresist onto said lower portion of said metal layer and said at least one bump via including to said sides and upper surface of said bump via, to form a lower electrical circuit pattern in said lower portion, said forming of said lower electrical circuit including removing said lower portion of said metal layer except for portions of said lower portion of said metal layer which form said electrical circuit pattern;
- forming an insulating layer on said lower electrical circuit and said at least one bump via;
- polishing said insulating layer to expose said upper surface of said at least one bump via;
- and
- forming an upper electrical circuit on said insulating layer in electrical contact with said at least one bump via.
Dependencies are inferred from the claim text.