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US 6,588,001 B1Granted
Method for inserting repeater cells in a deep sub-micron design
AssigneeMicron Technology, Inc.
InventorA. Kent Porterfield
Life of this patent
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Abstract
A method is provided in which repeater cells are automatically inserted within a sub-micron design before the physical design of the die has been started. The method automatically inserts a predetermined number of repeater cells within the interconnect lines that couple functional blocks on a semiconductor die. In a preferred embodiment, the repeater cell insertion is carried out during the logical design stage by adding a series of commands within a commercially available synthesis tool. A placement tool optimizes the physical placement of the repeater cells within the die.
Claims26
A method for automatically inserting repeater cells, the method comprising:
- operating a processing device to create a logic design to be incorporated onto a die the logic design including a plurality of levels of logical hierarchy, a first level of said logical hierarchy being made up of at least first and second functional blocks, wherein a logical representation of at least a first interconnect couples said first and second functional blocks;
- operating said processing device to create a new level of logical hierarchy, said new level of logical hierarchy being subordinate to said first level;
- and
- operating said processing device to automatically insert a logical representation of at least one repeater cell between an output port of said new level and an output port of said first functional block, such that said output port of said first functional block is coupled to both said logical representation of said at least one repeater cell and said logical representation of said first interconnect.
1 more element
A method for automatically inserting repeater cells, the method comprising:
- operating a processing device to create a logic design to be incorporated onto a die, the logic design including a plurality of levels of logical hierarchy, a first level of said logical hierarchy being made up of at least first and second functional blocks, wherein a logical representation of at least a first interconnect couples said first and second functional blocks;
- and
- operating said processing device to create a new level of logical hierarchy, said new level being subordinate to said first level;
- and
- operating said processing device to automatically insert a logical representation of at least one repeater cell between an input port of said new level and an input port of said first functional block, such that said input port of said first functional block is coupled to both said logical representation of said at least one repeater cell and said logical representation of said at least one interconnect.
2 more elements
A method for automatically inserting repeater cells, the method comprising:
- modifying an existing die creating synthesis program to implement a process, the process comprising the acts of:
- creating a logic design to be incorporated onto a die, the logic design including a plurality of levels of logical hierarchy, a first level of said logical hierarchy being made up of at least first and second functional blocks, wherein a logical representation of at least a first interconnect couples said first and second functional blocks;
- creating a new level of logical hierarchy, said new level of logical hierarchy being subordinate to said first level;
- and
- automatically inserting a logical representation of at least one repeater cell between an output port of said new level and an output port of said first functional block, such that said output port of said first functional block is coupled to both said logical representation of said at least one repeater cell and said logical representation of said first interconnect.
2 more elements
A computer readable storage medium storing a computer readable program or automatically inserting repeater cells, the program being configured to operate a computer to:
- create a logic design to be incorporated onto a die, the logic design including a plurality of levels of logical hierarchy, a first level of said logical hierarchy being made up of at least first and second functional blocks, wherein a logical representation of at least a first interconnect couples said first and second functional blocks;
- create a new level of logical hierarchy, said new level of logical hierarchy being subordinate to said first level;
- and
- automatically insert a logical representation of at least one repeater cell between an output port of said new level and an output port of said first functional block, such that said output port of said first functional block is coupled to both said logical representation of said at least one repeater cell and said logical representation of said first interconnect.
1 more element
A computer readable storage medium storing a computer readable program for automatically inserting repeater cells, the program being configured to operate a computer to:
- create a logic design to be incorporated onto a die, the logic design including a plurality of levels of logical hierarchy, a first level of said logical hierarchy being made up of at least first and second functional blocks, wherein a logical representation of at least a first interconnect couples said first and second functional blocks;
- create a new level in said logical hierarchy, said new level being subordinate to said first level;
- and
- automatically insert said logical representation of said at least one repeater cell between an input port of said new level and an input port of said first functional block, such that said input port of said first functional block is coupled to both said logical representation of said at least one repeater cell and said logical representation of said at least one interconnect.
1 more element
A processor system, comprising:
- at least one processor;
- and
- a storage medium coupled to said at least one processor, said storage medium storing a processor readable program for automatically inserting repeater cells, said at least one processor being responsive to said program to:
- create a logic design to be incorporated onto a die, the logic design including a plurality of levels of logical hierarchy, a first level of said logical hierarchy being made up of at least first and second functional blocks, wherein a logical representation of at least a first interconnect couples said first and second functional blocks;
- create a new level of logical hierarchy, said new level of logical hierarchy being subordinate to said first level;
- and
- automatically insert a logical representation of at least one repeater cell between an output port of said new level and an output port of said first functional block, such that said output port of said first functional block is coupled to both said logical representation of said at least one repeater cell and said logical representation of said first interconnect.
4 more elements
The processor system of 18, wherein said program is configured to operate said computer to synthesize a high level design language into a logical configuration.
A processor system, comprising:
- at least one processor;
- and
- a storage medium coupled to said at least one processor, said storage medium storing a processor readable program for automatically inserting repeater cells, said at least one processor being responsive to said program to:
- create a logic design to be incorporated onto a die, the logic design including a plurality of levels of logical hierarchy, a first level of said logical hierarchy being made up of at least first and second functional blocks, wherein a logical representation of at least a first interconnect couples said first and second functional blocks;
- create a new level in said logical hierarchy, said new level being subordinate to said first level;
- and
- automatically insert a logical representation of at least one repeater cell between an input port of said new level and an input port of said first functional block, such that said input port of said first functional block is coupled to both said logical representation of said at least one repeater cell and said logical representation of said at least one interconnect.
4 more elements
Dependencies are inferred from the claim text.