Method of partitioning large transistor design to facilitate transistor level timing

A system for partitioning a large transistor design including transistors and transistor networks, and of the type having a top hierarchical design level and a second, lower hierarchical design level, the system comprising:

• means for identifying a desired number of blocks for the second hierarchical level;
• means for representing the second hierarchical level as the desired number of blocks, each of the blocks having a boundary;
• means for identifying transistor networks that extend across block boundaries;
• means for re-assigning transistor networks that cross block boundaries into the top hierarchical level to reduce cross boundary transistor networks, and
• means for further re-assigning some of the transistors, that had been re-assigned back into the top hierarchical level, among the blocks to reduce the maximum number of transistors in any one block.

A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for partitioning a large transistor design including transistors and transistor networks, and of the type having a top hierarchical design level and a second, lower hierarchical design level, the method steps comprising:

• identifying a desired number of blocks for the second hierarchical level;
• representing the second hierarchical level as the desired number of blocks, each of the blocks having a boundary,
• identifying transistor networks that extend across block boundaries;
• re-assigning transistor networks that cross block boundaries into the top hierarchical level to reduce cross boundary transistor networks, and
• further re-assigning some of the transistors, that had been re-assigned back into the top hierarchical level, among the blocks to reduce the maximum number of transistors in any one block.