Modeling delays for small nets in an integrated circuit design
AssigneeLSI Logic Corporation
InventorsLei Chen, Sandeep Bhutani, Nianging Zhang
Life of this patent
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Abstract
A method of modeling delays in an integrated circuit design is disclosed that may be used to reduce the computation time of path delays in an integrated circuit design. A method of modeling delays in an integrated circuit design includes the steps of receiving as input a description of an integrated circuit design; identifying at least one small net in the integrated circuit design from the description; approximating an effective capacitance of the at least one small net by the total capacitance; and approximating an interconnect delay of the at least one small net by zero.
Claims23
A method of modeling cell delays in an integrated circuit design comprising the steps of:
- (a) receiving as input a description of an integrated circuit design;
- (b) identifying at least one small net in the integrated circuit design from the description;
- (c) approximating an effective capacitance of the at least one small net by a total capacitance;
- and
- (d) approximating an interconnect delay of the at least one small net by zero.
A computer program product comprising:
- a medium for embodying a computer program for input to a computer;
- and
- a computer program embodied in the medium for causing the computer to perform at least one of the following functions:
- (a) receiving as input a description of an integrated circuit design;
- (b) identifying at least one small net in the integrated circuit design from the description;
- (c) approximating an effective capacitance of the at least one small net by a total capacitance;
- and
- (d) approximating an interconnect delay of the at least one small net by zero.
A method of modeling cell delays in an integrated circuit design comprising the steps of:
- (a) receiving as input a description of an integrated circuit design;
- (b) calculating a wire resistance for each of a plurality of nets from the description;
- (c) calculating a total capacitance for each of the plurality of nets;
- (d) identifying a plurality of small nets in the plurality of nets;
- (e) approximating an effective capacitance for each of the plurality of small nets by the total capacitance;
- (f) approximating an interconnect delay for each of the plurality of small nets by zero;
- and
- (g) calculating a cell delay from the interconnect delay and the effective capacitance for each of the plurality of small nets.
Dependencies are inferred from the claim text.