Device and method for increased fault coverage using scan insertion techniques around synchronous memory

A method to test a circuit on a chip having memory, comprising:

• feeding a plurality of scan input signals into memory and a scan bypass circuit that bypasses memory, via a plurality of address, data and control inputs of the memory;
• logically combining at least ones of the plurality of address, data and control inputs in the scan bypass circuit to obtain a substantially equal plurality of scan bypass bits as a plurality of output bits output by the memory;
• using a multiplexer to receive the plurality of output bits of the memory and the substantially equal plurality of scan bypass bits of the scan bypass circuit;
• controlling the multiplexer to multiplex pass the substantially equal plurality of scan bypass bits of the scan bypass circuit and not the output bits from the memory when a scan test is run;
• and
• controlling the multiplexer to multiplex pass the plurality of output bits from the memory and not from the scan bypass circuit when the scan test is not run.
• 8.The method as recited in claim 7 comprising:
• comparing the bits passed against an expected value when the scan test is run;
• and
• reporting an error when the bits do not match the expected value when the scan test is run.

A device to test a circuit on a chip having memory, comprising:

• a memory embedded in the chip, the memory having a plurality of address, data and control inputs, and a plurality of output bits;
• scan bypass circuit means for logically combining at least ones of the plurality of address, data and control inputs to obtain a substantially equal plurality of scan bypass bits as the plurality of output bits output by the memory;
• and
• multiplexer means for receiving the plurality of output bits of the memory and the substantially equal plurality of scan bypass bits of the scan bypass circuit, wherein when a scan test is run the multiplexer means for multiplex passing the substantially equal plurality of scan bypass bits of the scan bypass circuit and not the output bits from the memory, and when the scan test is not run the multiplexer means for multiplex passing the plurality of output bits from the memory and not from the scan bypass circuit.

A device to test a circuit on a chip using a scan circuit, comprising:

• a sub-circuit portion embedded in the chip, the sub-circuit portion having a plurality of address, data and control inputs, and a plurality of output bits;
• a scan bypass circuit to logically combine at least ones of the plurality of address, data and control inputs to obtain a substantially equal plurality of scan bypass bits as the plurality of output bits output by the sub-circuit portion;
• and
• a multiplexer connected to receive the plurality of output bits of the sub-circuit portion and the substantially equal plurality of scan bypass bits of the scan bypass circuit, wherein when a scan test is run the multiplexer will multiplex pass the substantially equal plurality of scan bypass bits of the scan bypass circuit and not the output bits from the sub-circuit portion, and when the scan test is not run the multiplexer will multiplex pass the plurality of output bits from the sub-circuit portion and not from the scan bypass circuit.