Optimized metal stack strategy

A method for defining an optimized metal stack option, the method comprising the steps of:

• (a) using interconnect data from timing critical paths from at least one previous design to generate interconnect statistical data;
• (b) using the interconnect statistical data to vary physical properties of interconnects in a current design during simulation until optimum performance is achieved;
• (c) defining x common metal layers across at least two metal stack options, wherein interconnects on each of the metal layers have common physical and electrical characteristics;
• (d) defining an ASIC core design based on the x common metal layers, thereby making the ASIC core compatible with the different metal stack options;
• and
• (e) given custom ASIC designs, each having a total of y metal layers where y>x, fabricating respective custom ASICS using the ASIC core design and different ones of the metal stack options.

A method for defining an optimized metal stack option, the method comprising the steps of:

• (a) providing the metal stack with multiple layers including a top layer and at least two sublayers, when the sublayers include a middle layer and a bottom layer;
• (b) patterning bottom layer interconnects with a minimum thickness;
• (c) patterning middle and top layers interconnects with a thickness double that of the bottom layer interconnects;
• (d) patterning the bottom and middle layer interconnects with a base pitch;
• and
• (e) allowing the interconnects on the top layer to be patterned using either the base pitch or a double pitch.

An optimized metal stack option, comprising:

• multiple metal stack layers including a top layer and two sublayers, when the sublayers include a metal layer and a bottom layer;
• interconnects on the bottom layer patterned with a minimum thickness;
• interconnects on the middle and top layers patterned with a thickness double that of the bottom layer interconnects;
• and
• wherein the interconnects on the bottom and middle layers are patterned with a base pitch, while the top layer interconnects are patterned with either the base pitch or a double pitch.

A method for defining an optimized metal stack option, the method comprising the steps of:

• (a) using interconnect data from timing critical paths from at least one previous design to generate interconnect statistical data;
• (b) using the interconnect statistical data to vary thickness, width, and pitch of interconnects in a current design during simulation until optimum interconnect performance is achieved;
• and
• (c) patterning the interconnects within the metal stack option using a combination of two thicknesses and one pitch.

A method for reusing an ASIC core design with different metal stack options, the method comprising the steps of:

• (a) defining x common metal layers across at least two metal stack options, wherein interconnects on each of the metal layers have common physical and electrical characteristics;
• (b) defining an ASIC core design based on the x common metal layers, thereby making the ASIC core compatible with the different metal stack options;
• and
• (c) given custom ASIC designs, each having a total of y metal layers where y>x, fabricating respective custom ASICS using the ASIC core design and different ones of the metal stack options.

A method for reusing an ASIC core design with different metal stack options, the method comprising the steps of:

• (a) defining x common metal layers across the first and second metal stack option, wherein interconnects on each of the metal layers have common physical and electrical characteristics;
• (b) designing and fabricating a plurality of ASIC cores using the x common metal layers, thereby making the ASIC cores compatible with the different metal stack options;
• (c) fabricating a first custom ASIC by patterning the first metal stack option on top of a first one of the ASIC cores;
• and
• (d) fabricating a second custom ASIC by patterning the second metal stack option on top of a second one of the ASIC cores, thereby using a same ASIC core design with different metal stack options.