Apparatus and method of testing a semiconductor device

Semiconductor device testing apparatus for testing a semiconductor device, comprising:

• a pattern generator which, based on a predetermined control sequence, generates an input signal pattern that is to be input to the semiconductor device, and an expectation data signal pattern that is expected to be output from the semiconductor device with the input signal pattern having been input to the semiconductor device, wherein said pattern generator comprises:
• a pattern data memory which stores data of the input signal pattern and the expectation data signal pattern;
• a sequence control unit which generates the input signal pattern and the expectation data signal pattern by supplying an address signal to said pattern data memory, and stops an output of the address signal and thereafter resumes the output of the address signal based on the address set by the resuming address register in the event of a match-fail, wherein said sequence control unit further includes a fail-burst processing unit for performing a fail-burst process which stops an output of the address signal and repeatedly supplies the same input signal pattern to the semiconductor device in the event of the match fail;
• a comparison unit which compares an output signal pattern output from the semiconductor device and the expectation data signal pattern, and outputs a match signal in the event that the output signal is matched with predetermined data determined based on the expectation data signal pattern;
• said pattern generator including:
• a stoppage unit which stops the control sequence when said output signal pattern output from the semiconductor device does not match with said corresponding expectation pattern during a predetermined cycle;
• a resuming address register which temporally stores an address indicating where the control sequence is stopped;
• and
• a resuming unit which resumes the control sequence based on the address.

Semiconductor device testing apparatus for testing a semiconductor device, comprising:

• a pattern generator which, based on a predetermined control sequence, generates an input signal pattern that is to be input to the semiconductor device, and an expectation data signal pattern that is expected to be output from the semiconductor device with the input signal pattern having been input to the semiconductor device, wherein said pattern generator comprises:
• a pattern data memory which stores data of the input signal pattern and the expectation data signal pattern;
• a sequence control unit which generates the input signal pattern and the expectation data signal pattern by supplying an address signal to said pattern data memory, and stops an output of the address signal and thereafter resumes the output of the address signal based on the address set by the resuming address register in the event of a match-fail, wherein said sequence control unit further includes a fail-hold processing unit for performing a fail-hold process which stops an output of the address signal and an input of the input signal pattern to the semiconductor in the event of the match fail;
• a mode selector which selects one among any of a plurality of processes including the fail-hold process and a fail-burst process in the event of the match fail;
• a comparison unit which compares an output signal pattern output from the semiconductor device and the expectation data signal pattern, and outputs a match signal in the event that the output signal is matched with predetermined data determined based on the expectation data signal pattern;
• said pattern generator including:
• a stoppage unit which stops the control sequence when said output signal pattern output from the semiconductor device does not match with said corresponding expectation pattern during a predetermined cycle;
• a resuming address register which temporally stores an address indicating where the control sequence is stopped;
• and
• a resuming unit which resumes the control sequence from said address onto the other semiconductor devices.

A semiconductor device testing method of testing a plurality of semiconductor devices, comprising:

• generating, in accordance with a predetermined control sequence, an input signal pattern to be supplied to each of the plurality of the semiconductor devices, and a corresponding expectation data signal pattern to be output from each of the plurality of the semiconductor devices after the input signal pattern having been input to each of the plurality of the semiconductor devices;
• outputting a match signal in the event that an output signal pattern to be output from each of the plurality of the semiconductor devices is compared to the expectation signal pattern so that the output signal pattern is matched with a desired value determined based on the expectation data signal pattern;
• stopping the control sequence when said output signal pattern output from one of the plurality of the semiconductor devices does not match with said corresponding expectation data signal pattern during a predetermined match cycle;
• storing an address which indicates a position of where the control sequence is stopped;
• and
• resuming the control sequence from the address onto the other semiconductor devices.

A semiconductor device testing method of testing a semiconductor device, comprising:

• generating, in accordance with a predetermined control sequence, an input signal pattern to be supplied to the semiconductor device, and an expectation data signal pattern to be output from the semiconductor device after the input signal pattern having been input to the semiconductor device;
• outputting a match signal in the event that an output signal pattern to be output from the semiconductor device is compared to the expectation signal pattern so that the output signal pattern is matched with a desired value determined based on the expectation data signal pattern;
• stopping the control sequence in the event that a match fail when said output signal pattern output from the semiconductor device does not match with said corresponding expectation pattern during a predetermined match cycle;
• storing an address which indicates a resuming position of the control sequence;
• resuming the control sequence based on the address and;
• performing a fail-burst process by which to stop the control sequence and to repeatedly input the same input signal pattern to the semiconductor device in the event of the match fail.