Partitionable embedded circuit test system for integrated circuit
AssigneeCredence Systems Corporation
InventorsLawrence Kraus, Ivan-Pierre Batinic, Marc P. Loranger, Hiralal Ranga
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Abstract
A flexible built-in self-test (BIST) circuit is incorporated into an integrated circuit (IC) for testing one or random access memories or other memories embedded in an integrated circuit regardless of the number, size or test requirements of the memories. Input data from a controller that may be conveniently partitioned among components internal and external to the IC, supplies data to the BIST circuit indicating the size of the embedded memories to be tested and selecting from among several modes of BIST operation.
Claims16
An apparatus for testing a memory embedded in an integrated circuit (IC), wherein said memory includes a plurality of addressable memory cells and wherein said IC includes a logic circuit linked to said memory for read and write accessing said memory, the apparatus comprising:
- a test circuit included in said IC for receiving input MIN, MAX data and for successively testing all memory cells of said memory having addresses within a range of addresses indicated by said input MIN, MAX data to determine whether each memory cell is defective, and
- control means for supplying said MIN, MAX data to said test circuit,
- and further comprising switch means included in said IC for responding to an input MODE signal by disconnecting said logic circuit from said memory and by connecting said test circuit to said memory so that said test circuit can test the memory cells of said memory,
- wherein said test circuit pulses an output CERR signal whenever it determines one of said memory cells is defective,
- wherein said test circuit continuously asserts an output FAIL signal after determining that any one of said memory cells is defective,
- wherein said control means supplies a DIAG signal to said test circuit to tell it test said memory in a bit map mode,
- wherein when said test circuit tests said memory other than in said bit map mode, it asserts a DONE signal when it has completed testing all memory cells of said memory,
- wherein when said test circuit tests said memory in said bit map mode it pulses said DONE signal when it completes testing any one memory cell of said memory and waits until it receives a READY signal from said control means before testing a next memory cell of said memory,
- wherein said control means monitors said DONE signal to determine when said test circuit has completed a test.
An apparatus for testing a memory embedded in an integrated circuit (IC), wherein said memory includes a plurality of addressable memory cells and wherein said IC includes a logic circuit linked to said memory for read and write accessing said memory, the apparatus comprising:
- a test circuit included in said IC for successively testing all memory cells of said memory, pulsing an output CERR signal whenever it determines one of said memory cells is defective, and continuously asserting an output FAIL signal after determining that any one of said memory cells is defective, and wherein in response to a state of an input DIAG signal, said test circuit selectively either asserts a DONE signal when it has completed testing all of said memory cells or pulses said DONE signal each time it completes testing any one of said memory cells;
- and
- a control means for supplying said DIAG signal to said test circuit and for monitoring said DONE signal to determine when said test circuit has completed a test.
An apparatus for testing a plurality of memories embedded in an integrated circuit (IC), wherein each of said memories includes a plurality of addressable memory cells, wherein at least two of said memories have differing address ranges, and wherein said IC includes logic circuits linked to said memories for read and write accessing said memories, the apparatus comprising:
- a plurality of test circuits included in said IC, each corresponding to a separate one of said memories, for successively testing all memory cells of the corresponding memory having addresses within the corresponding memory's range of addresses as indicated by input MIN, MAX data to determine whether each memory cell is defective,
- control means for supplying said input MIN, MAX data to each of said test circuits,
- switch means included in said IC for responding to an input MODE signal by disconnecting said logic circuit from said memories and by connecting each said test circuit to its corresponding memory so that said test circuit can test the memory cells of its corresponding memory,
- wherein said control means also supplies said MODE control signal to said switch means,
- wherein each said test circuit pulses an output CERR signal whenever it determines one of said memory cells is defective and continuously asserts an output FAIL signal after determining that any one of said memory cells is defective,
- wherein said control means supplies a DIAG signal to each said test circuit, and
- wherein in response to a state of said DIAG signal, each said test circuit selectively either asserts an output DONE signal when it has completed testing all of said memory cells or pulses said DONE signal each time it completes testing any one of said memory cells.
An apparatus for testing a plurality of memories embedded in an integrated circuit (IC), wherein each memory includes a plurality of addressable memory cells and wherein said IC includes logic circuits linked to said memory for read and write accessing said memory, the apparatus comprising:
- a plurality of test circuits included in said IC, each corresponding to a separate one of said Memories, for successively testing all memory cells of the corresponding memory, pulsing an output CERR signal whenever it determines one of said memory cells is defective, and continuously asserting an output FAIL signal after determining that any one of said memory cells is defective, and wherein in response to a state of an input DIAG signal, said test circuit selectively either asserts a DONE signal when it has completed testing all of said memory cells or pulses said DONE signal each time it completes testing any one of said memory cells;
- glue logic,means for processing the DONE signal output of all of said test circuits to produce a single DONEX output signal, for processing the CERR output signals of all of said test circuits to produce a single CERRX output signal, and for processing the FAIL output signals of all of said test circuits to produce a single FAILX output signal,
- control means for supplying said DIAG signal to said test circuit and for monitoring said, CERRX, FAILX and DONEX.
Dependencies are inferred from the claim text.