Semiconductor device tester for measuring skew between output pins of a semiconductor device

A semiconductor device tester comprising:

• an interface that couples the semiconductor device tester to a plurality of output pins of a semiconductor device;
• a comparator circuit electrically coupled to at least two of the plurality of output pins of the semiconductor device that generates a skew signal having a duration corresponding to a time period between corresponding changes of data states of the plurality of output pins;
• and
• wherein the device tester includes a predetermined number of comparator circuits, each of the comparator circuits electrically coupled to different ones of the plurality of output pins and generating a skew signal having a duration corresponding to a time period when data on respective coupled ones of the plurality of output pins differs.

A semiconductor device tester comprising:

• a predetermined number of first circuits that generate an active signal when data on selected ones of a plurality of output pins of a semiconductor device differs and an inactive signal when the data on the selected ones of the plurality of output pins matches;
• a predetermined number of second circuits, each of the second circuits being associated with one of the first circuits, that generate an active signal when the data on the selected ones of the plurality of output pins matches and an inactive signal when the data on the selected ones of the plurality of output pins differs;
• and
• a predetermined number of flip flops, each of the flip flops having a set input electrically coupled to an associated one of the first circuits and a reset input electrically coupled to one of the second circuits associated with the associated one of the first circuits, each of the flip flops being configured to output a skew signal having a duration corresponding to a time period when data on the associated selected ones of the plurality of output pins differs.

A semiconductor device tester comprising:

• first signal generating means for generating on an output of the first signal generating means an active signal when data on two output pins of a semiconductor device differs and an inactive signal when the data matches;
• second signal generating means for generating on an output of the second signal generating means an active signal when the data matches and an inactive signal when the data differs;
• and
• third signal generating means for generating a skew signal corresponding to a time period when the data on the two output pins differs, the third signal generating means being set responsive to the output of the first signal generating means and reset responsive to the output of the second signal generating means.

A semiconductor device tester comprising:

• an interface that couples the semiconductor device tester to a plurality of output pins of a semiconductor device;
• a comparator circuit electrically coupled to at least two of the plurality of output pins of the semiconductor device that generates a skew signal having a duration corresponding to a time period between corresponding changes of data states of the plurality of output pins;
• wherein the comparator circuit further comprises:
• a first circuit that generates an active signal when the data on the at least two of the plurality of output pins differs and an inactive signal when the data on the at least two of the plurality of output pins matches;
• a second circuit that generates an active signal when the data on the at least two of the plurality of output pins matches and an inactive signal when the data on the at least two of the plurality of output pins differs;
• and
• a flip flop having a set input electrically coupled to the first circuit and a reset input electrically coupled to the second circuit that outputs the skew signal.