Semiconductor test apparatus and method
AssigneesMitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
InventorsHisaya Mori, Teruhiko Funakura
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Abstract
A semiconductor test apparatus and method for performing a test on a nonvolatile semiconductor memory such as a flash memory while preventing excessive erasing with reliability. In each erase operation, all addresses are scanned to fetch an error address and error data into a catch memory. Then, on the basis of error information (error address and error data), a rewrite operation is performed to write data on all memory cells. The write data varies according to a comparison result between an address signal and an error address signal. If they disagree, a “0” is written on a memory cell at the address. If they agree, a “0” is written on a “pass” memory cell and a “1” is virtually written on a fail memory cell.
Claims13
A semiconductor test apparatus comprising:
- a control signal generating unit configured to supply a control signal to at least one semiconductor memory under test so as to initiate a predetermined operation, said at least one semiconductor memory under test having a plurality of cells, said predetermined operation including an erase operation of setting each of said plurality of cells to a first value and a subsequent rewrite operation of setting a subset of said plurality of cells to a second value different from the first value;
- a judging unit configured to make a pass/fail judgment on each of said plurality of cells after said erase operation, where a cell having been set to said first value is judged as having passed and a cell not having been set to said first value is judged as having failed;
- and
- an error information storage unit configured to sequentially assign a semiconductor memory test address corresponding to each of said plurality of cells and to store a plurality of semiconductor memory test results, said semiconductor memory test results including a semiconductor memory error address corresponding to a cell judged by said judging unit as having failed, and corresponding error data, wherein
- said subset of said plurality of cells comprising a cell judged by said judging unit as having passed.
A semiconductor test method configured to determine whether a semiconductor memory has been successfully erased by a semiconductor test apparatus, including
- a control signal generating unit configured to supply a control signal to at least one semiconductor memory under test so as to initiate a predetermined operation, said at least one semiconductor memory under test having a plurality of cells, said predetermined operation including an erase operation of setting each of said plurality of cells to a first value and a subsequent rewrite operation of setting a subset of said plurality of cells to a second value,
- a judging unit configured to make a pass/fail judgement on each of said plurality of cells after said erase operation, where a cell having been set to said first value or successfully erased is judged as having passed and a cell not having been set to said first value or not having been successfully erased is judged as having failed, and
- an error information storage unit configured to sequentially assign a semiconductor memory test address corresponding to each of said plurality of cells and to store a plurality of semiconductor memory test results, said semiconductor memory test results including a semiconductor memory error address corresponding to a cell judged by said judging unit as having failed and corresponding error data,
- said semiconductor test method comprising the steps of:
- (a) performing said erase operation;
- (b) determining whether each of said plurality of cells was set to said first value so as to identify one of a successfully-erased cell and an unsuccessfully-erased cell;
- (c) storing said plurality of semiconductor memory test results;
- and
- (d) performing said rewrite operation only on said subset of said plurality of cells judged to have been successfully erased.
A semiconductor test method configured to determine whether a semiconductor memory has been successfully erased by a semiconductor test apparatus, including
- a control signal generating unit configured to supply a control signal to at least one semiconductor memory under test so as to initiate a predetermined operation, said at least one semiconductor memory under test having a plurality of cells, said predetermined operation including an erase operation of setting each of said plurality of cells to a first value and a subsequent rewrite operation of setting a subset of said plurality of cells to a second value different from the first value said subset of said plurality of cells being a set of cells judged by said judging unit as having passed,
- a judging unit configured to make a pass/fail judgment on each of said plurality of cells after said erase operation, where a cell having been set to said first value is judged as having passed and a cell not having been set to said first value is judged as having failed, and
- an error information storage unit configured to sequentially assign a semiconductor memory test address corresponding to each of said plurality of cells and to store a plurality of semiconductor memory test results, said semiconductor memory test results including a semiconductor memory error address corresponding to a cell judged by said judging unit as having failed, corresponding error data, and total error information including a number of fetched error addresses,
- said semiconductor test method comprising the steps of:
- (a) performing said erase operation;
- (b) acquiring said total error information from said error information storage unit;
- (c) making a pass/fail judgment on said at least one semiconductor memory under test on the basis of said total-error information;
- and
- (d) writing information about said semiconductor memory error address into said at least one semiconductor memory under test if said at least one semiconductor memory under test is judged to have passed in said step (c).
Dependencies are inferred from the claim text.