Semiconductor memory apparatus with power consumption control
AssigneeOki Electric Industry Co., Ltd.
InventorsShinji Hiratsuka, Kazuhiko Bando
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Abstract
A process controller 130 and clock controller 190 are used to detect transfer rates when performing data write and read operations involving memories 180-1 to 180-n for recording data. The clock controller 190 frequency-divides clock signals generated by an oscillator unit 191, thereby generating a plurality of frequency-divided clocks having different frequencies. One of the frequency-divided clocks is selected, according to the transfer rate detection results, and used as the operating clock for an interface unit 110, the process controller 130, a buffer unit 140, and a transfer controller 150. By altering the operating speeds of the circuits 110, 140, and 150, according to the data transfer rate, power consumption can be reduced.
Claims15
A semiconductor disk apparatus, comprising:
- a memory unit that stores data;
- a transfer circuit that transfers data input from an external apparatus to said memory unit and transfers data read from said memory unit to said external apparatus;
- an oscillator that generates fundamental clock signals of fixed frequencies;
- an operating clock supply circuit that selects the smallest frequency from divided frequencies of said fundamental clock signals that does not cause a delay of data transfer between said memory unit and said external apparatus, and supplies operating clock signals of the selected frequency to said transfer circuit;
- wherein said operating clock supply circuit selects the frequencies which do not cause a delay of data transfer, using a minimum high level time and a minimum low level time of read control signals and write control signals, wherein said read and write control signals are input from said external apparatus.
Dependencies are inferred from the claim text.