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US 6,587,954 B1Granted
Method and interface for clock switching
AssigneeAdvanced Micro Devices, Inc.
InventorKenny Kok-Hoong Chiu
Life of this patent
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Abstract
A clock switching technique allows selecting an input clock signal from any number of clock sources. Multiplexed input clock signals are switched on the fly onto an internal clock line coupled to an output clock line. Clock glitches are allowed on the output clock line. A clock invalid signal is asserted synchronous with the internal clock line during the time clock glitches may potentially be generated. The clock invalid signal signifies that clock switching is in progress and can be used to reset circuits which use the output clock line preventing problems in those circuits typically caused by clock glitches during the period of output clock instability. The clock switching technique is independent of clock source frequency as well as the system clock frequency.
Claims27
A clock selection device comprising:
- a first clock source selection logic adapted to select from a first plurality of input clock signals based on the value of a clock mode signal, producing an output clock line;
- a clock mode change tracking logic, the clock mode change tracking logic
- receiving a clock mode signal and a clock invalid signal and
- generating a clock mode change detect signal upon detection of a change in the clock mode signal,
- the clock mode change tracking logic
- deasserting the clock mode change detect signal upon an assertion of a synchronous clock invalid duration elapsed signal and
- asserting a synchronous clock invalid duration counter reset signal upon an assertion of the synchronous clock invalid duration elapsed signal;
- a clock mode change detect logic coupled to the clock mode change tracking logic, the clock mode change detect logic
- receiving the clock mode change detect signal, asserting a clock mode change signal upon detection of a change in the clock mode signal, and
- asserting a detect clock mode change complete signal upon a deassertion of the clock mode change detect signal;
- a clock invalid generation logic coupled to the clock mode change detect logic, the clock invalid generation logic
- receiving the clock mode change signal and the detect clock mode change complete signal,
- asserting a clock invalid signal to indicate the output clock line is unstable upon an assertion of the clock mode change signal, and
- deasserting the clock invalid signal to indicate the output clock line is stable upon an assertion of the clock mode change complete signal;
- and
- a synchronous clock invalid duration counter coupled to the first clock source selection logic, the synchronous clock invalid duration counter
- counting clock cycles on the internal clock line, and
- generating the synchronous clock invalid duration elapsed signal after counting a predetermined number of clock cycles on the output clock line,
- wherein the clock mode change detect signal enables the synchronous clock invalid duration counter,
- wherein the synchronous clock invalid duration counter is disabled and reset upon an assertion of the synchronous clock invalid duration counter reset signal, and
- wherein a synchronous reset signal synchronized with the output clock line resets the synchronous clock invalid duration counter.
18 more elements
A processor-based device comprising:
- a processor;
- a plurality of communication controllers coupled to the processor, each of the plurality of communication controllers comprising:
- a plurality of clock sources;
- and
- a clock selection device coupled to the plurality of clock sources adapted to select one of the plurality of clock sources for clocking the communications controller, the clock selection device comprising:
- a first clock source selection logic adapted to select from a first plurality of input clock signals based on the value of a clock mode signal, producing an output clock line;
- a clock mode change tracking logic, the clock mode change tracking logic
- receiving a clock mode signal and a clock invalid signal and
- generating a clock mode change detect signal upon detection of a change in the clock mode signal,
- the clock mode change tracking logic
- deasserting the clock mode change detect signal upon the assertion of a synchronous clock invalid duration elapsed signal and
- asserting a synchronous clock invalid duration counter reset signal upon the assertion of the synchronous clock invalid duration elapsed signal;
- a clock mode change detect logic coupled to the clock mode change tracking logic, the clock mode change detect logic
- receiving the clock mode change detect signal,
- asserting a clock mode change signal upon detection of a change in the clock mode signal, and
- asserting a detect clock mode change complete signal upon deassertion of the clock mode change detect signal;
- a clock invalid generation logic coupled to the clock mode change detect logic, the clock invalid generation logic
- receiving the clock mode change signal and the detect clock mode change complete signal,
- asserting a clock invalid signal to indicate the output clock line is unstable upon assertion of the clock mode change signal, and
- deasserting the clock invalid signal to indicate the output clock line is stable upon assertion of the clock mode change complete signal;
- and
- a synchronous clock invalid duration counter coupled to the first clock source selection logic, the synchronous clock invalid duration counter
- counting clock cycles on the internal clock line, and generating the synchronous clock invalid duration elapsed signal after counting a predetermined number of clock cycles on the output clock line,
- wherein the clock mode change detect signal enables the synchronous clock invalid duration counter,
- wherein the synchronous clock invalid duration counter is disabled and reset upon assertion of the synchronous clock invalid duration counter reset signal, and
- wherein a synchronous reset signal synchronized with the output clock line resets the synchronous clock invalid duration counter.
23 more elements
A method of selecting one of a plurality of clock sources onto a single output clock line, comprising the steps of:
- (a) receiving a plurality of input clock signals;
- (b) receiving a clock mode signal;
- (c) connecting one of the plurality of input clock signals to an internal clock line coupled to the output clock line;
- (d) dctecting a change in the clock mode signal;
- (e) asserting a clock invalid signal responsive to step (d);
- (f) switching a different input clock signal to the internal clock line responsive to step (d),
- (g) waiting a predetermined number of output clock cycles;
- and
- (h) deasserting the clock invalid signal,
- wherein the output clock line is unstable while the clock invalid signal is asserted.
7 more elements
A clock switching mechanism with guaranteed stability, comprising:
- a clock switching means for switching a clock source of a plurality of clock sources to an output clock line;
- a clock invalidation means for generating a clock invalid signal synchronous to a system clock to indicate when clock switching by the clock switching means is in progress,
- the output clock line being stable when the clock invalid signal is set to a first predetermined state indicating clock switching is complete and
- the output clock line being unstable when the clock invalid signal is set to a second predetermined state indicating clock switching is in progress;
- and
- a synchronous clock counting means for counting a duration if the clock invalid signal is set to the second predetermined state, the synchronous clock counting means being synchronous with the internal clock line.
3 more elements
Dependencies are inferred from the claim text.