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US 6,587,934 B2Granted
Memory controller and data processing system
AssigneeHitachi, Ltd.
InventorsSeiji Miura, Kazushige Ayukawa
Life of this patent
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Abstract
A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.
Claims11
A method of controlling a multi bank memory by a memory controller having a first mode and a second mode,
- wherein said memory is controlled to perform a precharge operation after a read access in said first mode,
- wherein said memory is controlled to receive a next access command without a precharge operation after a read access in said second mode,
- wherein, after a first number of successive times a different word line is selected, said memory controller changes said second mode to said first mode, and
- wherein said first number changes depending on access commands from a CPU.
1 more element
A method of controlling a memory by a memory controller having a first mode and a second mode,
- wherein said memory is controlled to close a page opened by a read access in said first mode,
- wherein said memory is controlled to leave the page opened until it receives a next access command in said second mode,
- wherein, after a first number of successive times a different page is selected, said memory controller changes said second mode to said first mode, and
- wherein said first number changes depending on access commands from a CPU.
1 more element
Dependencies are inferred from the claim text.