US 6,587,931 B1 · Directory-based cache coherency system supporting multiple instruction processor and input/output caches

Abstract

A directory-based cache coherency system is disclosed for use in a data processing system having multiple Instruction Processors (IP) and multiple Input/Output (I/O) units coupled through a shared main memory. The system includes one or more IP cache memories, each coupled to one or more IPs and to the shared main memory for caching units of data referred to as cache lines. The system further includes one or more I/O memories within ones of the I/O units, each I/O memory being coupled to the shared main memory for storing cache lines retrieved from the shared main memory. Coherency is maintained through the use of a central directory which stores status for each of the cache lines in the system. The status indicates the identity of the IP caches and the I/O memories having valid copies of a given cache line, and further identifies a set of access privileges, that is, the cache line “state”, associated with the cache line. The cache line states are used to implement a state machine which tracks the cache lines and ensures only valid copies of are maintained within the memory system. According to another aspect of the system, the main memory performs continuous tracking and control functions for all cache lines residing in the IP caches. In contrast, the system maintains tracking and control functions for only predetermined cache lines provided to the I/O units so that system overhead may be reduced. The coherency system further supports multiple heterogeneous instruction processors which operate on cache lines of different sizes.

Claims36

Dependent claims

In a data processing system having a main memory for storing addressable data signals, the main memory having at least a portion coupled to and shared by multiple requesters including one or more requesters of a first type and one or more requesters of a second type, each of the requesters having local memory capable of storing valid copies of requested ones of the data signals stored in the shared main memory, the improvement, comprising:

a coherency system having a central directory storage unit to store associated status bits associated with selected ones of the data signals, said associated status bits indicating the identity of the various requesters storing valid copies of associated requested ones of the data signals, said status bits further indicating the type of access privileges that are associated with each of said valid copies of said associated requested ones of the data signals, said type of access privileges being selected from a first set of access privileges for the data signals stored by one or more of the first type of requesters and said type of access privileges being selected from a different second set of access privileges for copies of the data signals stored by one or more of the second type of requesters.

For use in a data processing system having multiple instruction processors (IPs) and multiple input/output (I/O) systems, a memory system, comprising:

a shared main memory to store addressable blocks of data signals;
one or more IP caches each coupled to one or more of the IPs and each coupled to said shared main memory to store selectable ones of said addressable blocks of data signals received from said shared main memory;
one or more I/O memories each coupled to an associated one or more of the I/O systems and each coupled to said shared main memory to store selectable ones of said addressable blocks of data signals received from said shared main memory;
a central directory storage device coupled to said shared main memory to store directory information for each associated one of said addressable blocks, said directory information indicating which of said one or more IP caches and which of said one or more I/O memories is storing an associated addressable block of data signals, said directory information further including access privilege indicators for said associated addressable block of data signals, said access privilege indicators being selected from a first set of access privilege indicators if at least one of said IP caches stores said associated_addressable block, said access privilege indicators being selected from a second set of access privilege indicators if only said one or more I/O memories stores said associated addressable block.

1 more element

In a data processing system having a shared main memory to store addressable blocks of data signals and coupled to multiple requesters, one or more of the requesters being of a first type and one or more of the requesters being of a second type, each of the first and second type of requesters having associated local memory capable of storing requested blocks of data signals, the requesters of the first type to submit requests of a first type to the shared main memory and the requesters of the second type to submit requests of a second type to the shared main memory, ones of the first and second types of requests are each indicative of a request to have access to valid copies of requested ones of the addressable blocks of data signals, a coherency system, comprising:

a central directory storage system coupled to the shared main memory to store status bits associated with each of the addressable blocks of data signals stored within the shared main memory, associated ones of said status bits indicating the identity and type of each of the requesters having a valid copy of said associated addressable block of data signals, and other associated ones of said status bits indicating the state of said associated addressable block of data signals, wherein said state defines the type of allowable operations which may be performed to valid copies of said associated addressable block of data signals and to said associated addressable block of data signals stored in the shared main memory;
a request selection circuit coupled to ones of the requesters of the first type and ones of requesters of the second type to receive requests of the first type and requests of the second type, respectively, and to select one of said received requests as a selected request;
a state control circuit coupled to said directory storage system to receive ones of said status bits and coupled to said request selection circuit to receive said selected request, said state control circuit capable of issuing a selected one of a predetermined first set of coherency functions in response to a request of the first type, and of issuing a selected one of a predetermined second set of coherency functions in response to a request of the second type, said state control circuit to determine, based on said state of a requested one of the addressable blocks, based on said identity and type of the requesters having a valid copy of said requested one of the addressable blocks, and further based on said type of selected request, which one of said coherency functions said state control circuit is to perform prior to providing a valid copy of said requested one of the addressable blocks to grant said selected request.

central directory storage means coupled to the shared main memory for storing status bits associated with each of the addressable blocks of data signals stored within the shared main memory, associated ones of said status bits for indicating the identity and type of each of the requesters having a valid copy of said associated addressable block of data signals, and other associated ones of said status bits for indicating the state of said associated addressable block of data signals, wherein said state is based on the type of requester having a valid copy of said associated addressable block of data signals, and defines the type of allowable coherency functions which may be performed to valid copies of said associated addressable block of data signals and to said associated addressable block of data signals stored in the shared main memory;
request selection means coupled to ones of the requesters of the first type and ones of requesters of the second type for receiving requests of the first type and requests of the second type, respectively, and for selecting one of said received requests as a selected request;
state control means coupled to said directory storage means for receiving ones of said status bits and coupled to said request selection means for receiving said selected request, said state control means for issuing a predetermined set of said coherency functions, said state control means for determining, based on said state of a requested one of the addressable blocks, based on the type of the requesters having a valid copy of said requested one of the addressable blocks, and further based on said selected request, which one of said predetermined set of coherency functions said state control means is to perform prior to providing a valid copy of said requested one of the addressable blocks to grant said selected request.

Dependencies are inferred from the claim text.

Directory-based cache coherency system supporting multiple instruction processor and input/output caches

Life of this patent

Directory-based cache coherency system supporting multiple instruction processor and input/output caches

Life of this patent

Abstract

Claims36