Apparatus and method for performing write-combining in a pipelined microprocessor using tags

An apparatus in a processor for determining whether first data of a first store operation may be combined with second data of a second store operation into a single write operation on a bus coupled to the processor, the first and second data having first and second addresses, respectively, the apparatus comprising:

• tag allocation logic, for allocating a first tag to the first data based on a comparison of the first address with the second address;
• a tag comparator, coupled to said tag allocation logic for comparing said first tag with a second tag previously allocated by said tag allocation logic to the second data;
• and
• write-combine logic, coupled to said tag comparator, for determining whether the first and second data may be combined based on said tag comparator comparing said first and second tags.

A write-combining processor, comprising:

• an address register, for storing a last write-combinable store address;
• a tag register, coupled to said address register, for storing a last write-combinable store tag;
• a comparator, coupled to said address register, for comparing said last write-combinable store address with a new store address of new store data;
• tag allocation logic, coupled to said comparator, for allocating a new tag to said new store data, wherein said tag allocation logic allocates said last write-combinable store tag to said new store data if said last write-combinable store address matches said new store address, and allocates a different tag than said last write-combinable store tag if said last write-combinable store address does not match said new store address;
• a plurality of write buffers, for buffering an associated plurality of data for writing to memory on a bus coupled to the processor;
• a plurality of tag registers, coupled to said plurality of write buffers, for storing a plurality of tags associated with said plurality of data;
• and
• a plurality of tag comparators, coupled to said plurality of tag registers, for comparing said new tag with said plurality of tags;
• wherein the processor selectively combines said new store data with one of said plurality of data buffered in said plurality of write buffers prior to writing to said memory on said bus based on said comparing by said plurality of tag comparators.

A method for performing write-combining in a microprocessor having a pipeline of stages, the method comprising:

• generating a first tag for first store data;
• comparing a first bus address of said first store data with a second bus address of second store data after said generating said first tag;
• generating a second tag for second store data in response to said comparing said first and second bus addresses;
• comparing said first and second tags;
• and
• selectively combining said first and second data based on said comparing said first and second tags.