Dual line size cache directory

In a computer system having a processor, a memory system including multiple levels of caches L1, L2, . . . , Ln−1 and including main memory Ln, and in which the cache Li−1 includes lines of size s and the cache Li−2 includes lines of size r with s>r, a cache directory system for the contents of cache Li−1 comprising:

• a dual line size cache directory structure including:
• a) a first mechanism for determining whether said cache Li−1 includes a line of size s corresponding to address A, and,
• b) a second mechanism for determining whether said cache Li−1 includes any of the t/s lines of size s residing in the larger line of size t corresponding to said address A in said cache level Li said address A including tag and offset information utilized by said second mechanism for determining the locations and status of said t/s lines of size s residing in said larger line of size t simultaneously in said cache Li−1 directory structure;
• and,
• c) batched writeback mechanism wherein, responsive to determination of a single line of size s in cache level Li−1 having a modified status, said batched writeback mechanism determining whether there exists other (t/s )−1 lines of size s residing in the larger line of size t that have a modified status, and concurrently writing back said one or more lines of size s that have been modified in said cache level Li−1 to said cache level Li.

In a computer system having a processor, a memory system including multiple levels of caches L1, L2, . . . , Ln−1 and including main memory Ln, and in which the cache level Li−2 includes lines of size r, the cache level Li−1 includes lines of size s and the cache Li includes lines of size t with r<s<t, a cache directory system for the contents of cache Li−1, and Li−2 comprising:

• a dual line size cache directory structure including:
• a) a first mechanism for determining whether said cache Li−1 includes a line of size s corresponding to address A, and,
• b) a second mechanism for determining whether said cache Li−1 includes any of the t/s lines of size s residing in the larger line of size t corresponding to said address A in said cache level Li said address A including tag and offset information utilized by said second mechanism for determining the locations and status of said tis lines of size s residing in said larger line of size t simultaneously in said cache Li−1 directory structure;
• and,
• a mechanism adhering to an inclusion property wherein, responsive to eviction of a line of size s in cache level Li−1 that is to be replaced with new data contents, said inclusion mechanism concurrently and simultaneously modifying a status of each of the s/r lines residing in said cache level Li−2 associated with said cache level Li−1 line as invalid in said cache level Li−2 directory.