Multiprocessor system
AssigneeHitachi, Ltd.
InventorsTatsuo Higuchi, Shinichi Kawamoto, Naoki Hamanaka
Life of this patent
Estimating the term…
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AssigneeHitachi, Ltd.
InventorsTatsuo Higuchi, Shinichi Kawamoto, Naoki Hamanaka
Estimating the term…
A multiprocessor system can reduce a broadcast for cache memory consistency control with memory access from an I/O device. The multiprocessor system is provided with a cache memory identifier or an owner tag, and a block length table for recording a memory write block length of the I/O device. The cache memory identifier records that the cache has an exclusive copy. The owner tag records that there is no cache memory having an exclusive copy. If there is an exclusive copy during read through the I/O device, a read request is issued to both a cache holding the copy and a memory. If it is recorded that the copy is not present, data are directly read from the memory. Moreover, when a write block length is recorded in the block length table during write, whole blocks are collected to issue a request for invalidation from the cache and the request is directly written to the memory after the invalidation is completed.
A multiprocessor system having at least one processor and a cache memory per the at least one processor, the multiprocessor comprising a sharing memory type multiprocessor wherein a plurality of nodes having both the at least one processor and the cache memory, and a plurality of I/O devices share a memory through a network,
Dependencies are inferred from the claim text.