Method and apparatus for reducing latency in a memory system
AssigneeMosaid Technologies Incorporated
InventorNagi Nassief Mekhiel
Life of this patent
Estimating the term…
Abstract
A memory controller controls a buffer which stores the most recently used addresses and associated data, but the data stored in the buffer is only a portion of a row of data (termed row head data) stored in main memory. In a memory access initiated by the CPU, both the buffer and main memory are accessed simultaneously. If the buffer contains the address requested, the buffer immediately begins to provide the associated row head data in a burst to the cache memory. Meanwhile, the same row address is activated in the main memory bank corresponding to the requested address found in the buffer. After the buffer provides the row head data, the remainder of the burst of requested data is provided by the main memory to the CPU.
Claims14
A method of retrieving data from a memory system, said method comprising:
- (a) receiving a read request for data contents of a memory location;
- (b) searching a buffer portion of said memory system for a portion of said data contents;
- (c) in the event that said portion of said data contents is stored in said buffer, retrieving said portion from said buffer while concurrently retrieving a remaining portion of said data contents from a main memory portion of said memory system;
- and
- (d) in the event that said portion of said data contents is not stored in said buffer, retrieving said portion and said remaining portion of said data contents from main memory.
A row head buffer circuit for latching a row head, a row head being a portion of a memory row stored in a memory bank, said latching circuit comprising:
- a row head buffer containing a plurality of row head entries, each row head entry corresponding to a row head in a memory bank;
- a plurality of row address latches, each row address latch latching a physical address of a row head entry contained in the row head buffer;
- a row address comparator for comparing row head entries with an incoming requested row address,
- wherein
- said buffer circuit compares an incoming row address requested by a memory controller with said plurality of row address latches, in the event an incoming requested row address matches one of said plurality of address latches, a row head data entry corresponding to a matching address latch is transmitted to said memory controller.
A memory buffer subsystem comprising:
- at least one buffer bank having multiple buffer entries;
- and
- a buffer controller controlling said buffer subsystem,
- wherein
- each buffer entry comprises:
- an address field containing a memory address corresponding to a location in a main memory bank;
- a data field containing the first n bytes of data is located at said main memory bank address;
- when said data located at said main memory bank address is requested by a CPU, said first n bytes of data is provided by said buffer subsystem to said CPU while the rest of said data is retrieved from said memory address in the main memory bank.
Dependencies are inferred from the claim text.