Memory architecture for supporting concurrent access of different types
AssigneeAgilent Technologies, Inc.
InventorLaura Elisabeth Simmons
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Abstract
A memory architecture for supporting mixed-mode memory accesses. A common row address is provided. A first column address for accessing a first column and a second column address for accessing a second column are provided. A first write control signal for specifying one of a write access and a read access for the first column, and a second write control signal for specifying one of a write access and a read access for the second column are also provided. The memory architecture, responsive to these input signals, supports concurrent mixed-mode memory accesses to the first column and a write access to the second column.
Claims14
As A method for performing mixed-mode memory accesses for different columns in a common row comprising the steps of:
- a) providing a row address for specifying a first row;
- b) providing a first column address for accessing a first column in the first row;
- c) providing a second column address for accessing a second column in the first row;
- d) providing a first write control signal for specifying one of a write access and a read access for the first column;
- e) providing a second write control signal for specifying one of a write access and a read access for the second column;
- and
- f) providing concurrent mixed-mode memory accesses to the first column in the first row and to the second column in the first row.
A memory comprising:
- a) a first column space that is assigned to a first functional block;
- b) a second column space that is assigned to a second functional block;
- c) a first column address signal for accessing the first column space;
- d) a second column address signal for accessing the second column space;
- e) a first write signal for specifying one of a write access and a read access for the first column;
- and
- f) a second write signal for specifying one of a write access and a read access for the second column;
- wherein the memory supports concurrent mixed mode accesses of the first column and the second column of a common row.
Dependencies are inferred from the claim text.