Interleaved memory device for burst type access in synchronous read mode with the two semi-arrays independently readable in random access asynchronous mode

An interleaved memory comprising:

• an array of memory cells divided into a first bank of memory cells and a second bank of memory cells;
• first and second address counters respectively coupled to said first and second banks of memory cells;
• an address transition detector circuit for generating an address transition detecting signal based upon a change of an address acquired during a random access asynchronous read mode and upon generation of an increment pulse by one of said first and second address counters in a sequential access synchronous read mode;
• first and second decoding circuits respectively coupled to said first and second banks of memory cells;
• first and second reading circuits respectively coupled to said first and second banks of memory cells;
• a plurality of output data buffers coupled to said first and second reading circuits, and having inputs for receiving data therefrom based upon a load signal specific to one of said first and second banks of memory cells;
• and
• a control circuit connected to said plurality of output data buffers and having inputs for receiving a first external command signal and a second external command signal for enabling the interleaved memory, for generating the load signal and for discriminating a reading mode requested from a protocol of use, and
• a transition to a first logic state for the first external command signal enables acquisition of an input address and starts a new random access asynchronous read mode with a simultaneous activation of said respective reading circuits, and a transition to a second logic state for the first external signal causes switching to the sequential access synchronous read mode by generating within said control circuit a first increment pulse for one of said first and second address counters not in priority, and the second external command signal functions as a clock for transferring data read from said first or second bank of memory cells currently in priority.

An interleaved memory for operating in a sequential access synchronous read mode and in a random access asynchronous read mode and comprising:

• an array of memory cells divided into a first bank of memory cells and a second bank of memory cells;
• first and second decoding circuits respectively coupled to said first and second banks of memory cells;
• first and second reading circuits respectively coupled to said first and second banks of memory cells;
• a plurality of output data buffers coupled to said first and second reading circuits, and having inputs for receiving data therefrom based upon a load signal specific to one of said first and second banks of memory cells;
• and
• a control circuit connected to said plurality of output data buffers and having inputs for receiving a first external command signal and a second external command signal for enabling the interleaved memory, for generating the load signal and for discriminating a reading mode requested from a protocol of use.

A method for reading an interleaved memory in a sequential access synchronous read mode and in a random access asynchronous read mode, the interleaved memory comprising an array of memory cells divided into a first bank of memory cells and a second bank of memory cells;

• first and second address counters respectively coupled to the first and second banks of memory cells;
• first and second decoding circuits respectively coupled to said first and second banks of memory cells;
• first and second reading circuits respectively coupled to said first and second banks of memory cells;
• and a plurality of output data buffers coupled to the first and second reading circuits;
• the method comprising:
• generating an address transition detecting signal based upon a change of an address acquired during the random access asynchronous read mode and upon generation of an increment pulse by one of the first and second address counters in the sequential access synchronous read mode;
• transferring data stored in the first and second reading circuits to the plurality of output data buffers based upon a load signal specific to one of the first and second banks of memory cells;
• and
• enabling the interleaved memory, generating the load signal and discriminating a reading mode requested from a protocol of use based upon a first external command signal and a second external command signal.