Method and apparatus for implementing multiple memory buses on a memory module
AssigneeIntel Corporation
InventorsMichael W. Leddige, Bryce D. Horine, Randy Bonella, Peter D. MacWilliams
Life of this patent
Estimating the term…
Abstract
A computer system memory module includes a bi-directional repeater hub that in a first direction takes as an input a memory bus signal in a first port, regenerates the memory signals, and outputs the regenerated memory signal at a second port as at least one separate signal for coupling to a memory bus for each of the regenerated separate signals. In a second direction, the bi-directional repeater hub takes as input at least one memory bus signal at the second port, regenerates each input memory bus signal, and outputs the regenerated memory signal at the first port for coupling to a memory bus.
Claims32
A memory module, comprising:
- a first memory bus to transmit memory signals on and off the memory module;
- a second memory bus to transmit the memory signals to a plurality of memory devices on the memory module;
- and
- a memory repeater coupled to the first and second memory buses, the memory repeater to determine whether the memory signals received via the first memory bus are to be transmitted to the plurality of memory devices via the second memory bus, and the memory repeater to determine whether to direct the memory signals off the memory module to another memory module via the first memory bus.
A computer system, comprising:
- a bus;
- a processor coupled to the bus;
- a memory controller coupled to the bus;
- a first memory bus to transmit memory signals from the memory controller;
- and
- a memory system, that includes a first memory module coupled to the memory controller via the first memory bus, the first memory module having a second memory bus connected with the first memory bus via a memory repeater, wherein the memory repeater is to determine whether the memory signals received via the first memory bus are to be transmitted to the first memory module via the second memory bus, and the memory repeater to determine whether to direct the memory signal to a second memory module via the first memory bus.
A memory module, comprising:
- a first memory bus to transmit memory signals on and off the memory module;
- a second memory bus to transmit the memory signals to a first plurality of memory devices;
- a third memory bus, connected in parallel with the second memory bus, to transmit the memory signals to a second plurality of memory devices on the memory module;
- and
- a memory repeater coupled to the first, second, and third memory buses to determine whether the memory signals received via the first memory bus are to be transmitted to the first or second plurality of memory devices via the second or third memory buses, or to be routed off the memory module via the first memory bus.
Dependencies are inferred from the claim text.