Universal serial bus PC synchronization algorithm for peripheral devices
AssigneeDell Products L.P.
InventorsMark A. Larson, Benjamen G. Tyner
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Abstract
Provided is a method, a computer program product, and a computer system each of which features queuing data transfers between a data port and a system memory to minimize the latency between queuing a data transfer and effectuating the transfer of the same and to remove the chance of more than one device trying to talk to the OS at the same time through the same port. This facilitates backwards compatibility of non-USB compatible computer resources, such as applications, operating systems (O/S) and the like, with USB compatible peripheral devices.
Claims28
A method of transferring data between a port and a system memory in a computer system, said method comprising:
- classifying multiple data transfers between said port and said system memory as being one of a plurality of classifications, defining a plurality of classified transfers;
- assigning each of said plurality of classified transfers to one of a plurality of queues dependent upon the classification, among said plurality of classifications, associated therewith, with each of said plurality of queues comprising a group of addresses in said system memory;
- and
- transmitting said plurality of classified transfers between said port and said system memory sequentially, defining a transfer sequence, with a position of each of the plurality of classified transfers in said transfer sequence being dependent upon a predetermined set of parameters.
A computer program product to transfer data between a port and a system management memory in a computer system, said computer program product comprising:
- code to classify multiple data transfers between said port and said system memory as being one of a plurality of classifications, defining a plurality of classified transfers;
- code to assign each of said plurality of classified transfers to one of a plurality of queues dependent upon the classification, among said plurality of classifications, associated therewith, with each of said plurality of queues comprising a group of addresses in said system memory;
- and
- code to transmit said plurality of classified transfers between said port and said system memory sequentially, defining a transfer sequence, with a position of each of the plurality of classified transfers in said transfer sequence being dependent upon a predetermined set of parameters.
A computer system comprising:
- a memory having a program stored therein;
- a port in data communication with said memory communication bus;
- a plurality of I/O devices in data communication with said port;
- a processor, in data communication with said memory and said port plurality of I/O devices, with said program including program code to classify multiple data transfers between said port and said system memory as being one of a plurality of classifications, defining a plurality of classified transfers and assign each of said plurality of classified transfers to one of a plurality of queues dependent upon the classification, among said plurality of classifications, associated therewith, with each of said plurality of queues comprising a group of addresses in said system memory;
- and transmit said plurality of classified transfers between said port and said system memory sequentially, defining a transfer sequence, with a position of each of the plurality of classified transfers in said transfer sequence being dependent upon a predetermined set of parameters.
Dependencies are inferred from the claim text.