Impedance matching device for high speed memory bus

A memory bus comprising:

• a functional memory module;
• and
• a memory bus impedance matching module populated only with non-functional dynamic random access memory packages having an operable power supply line and defective address lines, the memory bus impedance matching module exhibiting an impedance substantially equal to that of the functional memory module.

A method of reducing errors in a memory bus connected to a microprocessor when at least one expansion socket on the memory bus is empty and at least one functional memory module is coupled to the bus, the method comprising:

• installing in each empty expansion socket on the memory bus a memory bus impedance matching module populated only with non-functional dynamic random access memory packages having an operable power supply line and internal fuses programmed to disconnect the power supply line, the memory bus impedance matching module having an impedance substantially equal to that of the functional memory module.

A method of making a memory bus impedance matching module comprising:

• testing memory devices and identifying certain memory devices which are non-functional and exhibit an impedance substantially similar to that of a functional memory device, the non-functional memory devices having a defective power supply line;
• and
• mounting only the non-functional memory devices on a module housing adapted to fit into a memory expansion socket of a computer memory bus.

A memory bus impedance matching module comprising:

• a module housing adapted to fit into a memory expansion socket of a computer memory bus, the module housing having locations for mounting N impedance devices and including communication line connections suitable for coupling to the computer memory bus;
• and
• N impedance devices having memory circuitry having an operable power supply line and defective address lines, the N impedance devices mounted on the module housing and coupled to the communication line connections, wherein the memory bus impedance matching module exhibits an impedance substantially equal to that of a functional memory module adapted to fit into the memory expansion socket.

A memory bus comprising:

• a functional memory module;
• and
• a non-functional memory module populated only with impedance devices having a defective power supply line and exhibiting an impedance substantially equal to that of the functional memory module.

A memory bus impedance matching module comprising:

• a module housing adapted to fit into a memory expansion socket of a computer memory bus, the module housing having locations for mounting N impedance devices and including communication line connections suitable for coupling to the memory bus;
• and
• N impedance devices having an operable power supply line and defective data input/output lines, the N impedance devices exhibiting an impedance substantially equal to that of memory devices on a functional memory module adapted to fit into the memory expansion socket and the N impedance devices mounted on the housing and coupled to the communication line connections.

A memory bus comprising:

• a functional memory module;
• and
• a memory bus impedance matching module populated only with defective memory devices having an operable power supply line and defective data input/output lines, the memory bus impedance matching module exhibiting an impedance substantially equal to that of the functional memory module.

A method of reducing errors in a memory bus connected to a microprocessor when at least one expansion socket on the memory bus is empty and at least one functional memory module is coupled to the bus, the method comprising:

• installing in each empty expansion socket on the memory bus a memory bus impedance matching module populated only with non-functional memory devices having defective power supply lines, the impedance matching module having an impedance substantially equal to that of the functional memory module.

A memory bus impedance matching module comprising:

• a module housing adapted to fit into a memory expansion socket of a computer memory bus, the module housing having locations for mounting N impedance devices and including communication line connections suitable for coupling to the computer memory bus;
• and
• N impedance devices comprising non-functional dynamic random access memory dice having a defective power supply line, the N impedance devices mounted on the module housing and coupled to the communication line connections, wherein the memory bus impedance matching module exhibits an impedance substantially equal to that of a functional memory module adapted to fit into the memory expansion socket.