Computer system having peer-to-peer bus bridges and shadow configuration registers

A computer system configured to process transaction. requests, comprising:

• a processor programmed with an operating system having computer instructions to cause the processor to issue a plurality of configuration commands that include configuration data representing a range of addresses assigned to a first bus device;
• a host bus coupled to the first bus device and the processor to carry the configuration commands;
• a second bus bridge coupled to the host bus, the second bus bridge being structured to store the configuration data for the first bus device and, in response to receiving from the processor via the host bus a transaction request directed to an address with the range of addresses assigned to the first bus device, determine that the second bus bridge should not transmit a response to the transaction request based on the configuration data in the second bus bridge;
• and
• a third bus bridge coupled between the second bus bridge and a peripheral bus, the second bus device being structured to forward a transaction request from the host bus to the third bus bridge via the second bus bridge in response to determining that the transaction request is directed to other than the first bus device based on the configuration data stored in the second bus bridge.

A computer bus device for a computer system that includes a host bus to couple the computer bus device and an alternate computer bus device to a processor of the computer system, the computer bus device comprising:

• a first configuration register to store configuration information regarding the computer bus device;
• a second configuration register to store configuration information regarding the alternate computer bus device;
• and
• a target interface coupled to the host bus, the target interface being structured to receive a configuration command from the processor, determine whether the configuration command includes configuration information regarding the computer bus device or the alternate computer bus device, cause the configuration information to be stored in the first configuration register if the configuration information is regarding the computer bus device, and cause the configuration information to be stored in the second configuration register if the configuration information is regarding the alternate computer bus device, the target interface being structured to forward a transaction request from the host bus in response to determining that the transaction request is directed to other than the alternate computer bus device.

A computer system configured to process transaction requests, comprising;

• a processor programmed to issue a plurality of configuration commands;
• a host bus coupled to the processor to carry the configuration commands;
• a first bus bridge directly coupled to the processor by the host bus, the first bus bridge including at least one configuration register structured to store configuration data regarding the first bus bridge, the configuration data being received from the processor in at least one of the configuration commands;
• and
• a second bus bridge directly coupled to the processor by the host bus, the second bus bridge including a first set of configuration registers structured to store configuration data regarding the second bus bridge and a second set configuration registers structured to store the configuration data regarding the first bus bridge, the second bus bridge being coupled to the host bus with the same hierarchy as the first bus bridge.

A computer system configured to process transaction requests, comprising:

• a processor programmed to issue a plurality of configuration commands;
• a host bus coupled to the processor to carry the configuration commands;
• a first bus bridge coupled to the processor by the host bus without any intervening bus bridges, the first bus bridge including at least one configuration register structured to store configuration data regarding the first bus bridge, the configuration data being received from the processor in at least one of the configuration commands;
• and
• a second bus bridge coupled to the processor by the host bus without any intervening bus devices, the second bus bridge including a first set of configuration registers structured to store configuration data regarding the second bus bridge and a second set configuration registers structured to store the configuration data regarding the first bus bridge, the second bus bridge being coupled to the host bus with the same hierarchy as the first bus bridge.

A computer system configured to process transaction requests, comprising:

• a processor programmed to issue a plurality of configuration commands that include configuration data representing a range of addresses assigned to a first bus device;
• a host bus directly coupled to the first bus device and the processor to carry the configuration commands;
• a second bus bridge directly coupled to the host bus, the second bus bridge being structured to store the configuration data for the first bus device and, in response to receiving from the processor via the host bus a transaction request directed to an address within the range of addresses assigned to the first bus device, determine that the second bus bridge should not transmit a response to the transaction request based on the configuration data stored in the second bus bridge;
• and
• a third bus bridge coupled between the second bus bridge and a peripheral bus, the second bus device being structured to forward a transaction request from the host bus to the third bus bridge via the second bus bridge in response to determining that the transaction request is directed to other than the first bus device based on the configuration data stored in the second bus bridge.

A computer system configured to process transaction requests, comprising:

• a processor programmed to issue a plurality of configuration commands that include configuration data representing a range of addresses assigned to a first bus device;
• a host bus coupled to the first bus device and the processor to carry the configuration commands, wherein the first bus device is coupled to the host bus without any intervening bus devices;
• a second bus bridge coupled to the host bus without any intervening bus bridges, the second bus bridge being structured to store the configuration data for the first bus device and, in response to receiving from the processor via the host bus a transaction request directed to an address with the range of addresses assigned to the first bus device, determine that the second bus bridge should not transmit a response to the transaction request based on the configuration data stored in the second bus bridge;
• and
• a third bus bridge coupled between the second bus bridge and a peripheral bus, the second bus device being structured to forward a transaction request from the host bus to the third bus bridge via the second bus bridge in response to determining that the transaction request is directed to other than the first bus device based on the configuration data stored in the second bus bridge.

A computer bus device for a computer system that includes a host bus to couple the computer bus device and an alternate computer bus device to a processor of the computer system, the computer bus device comprising:

• a first configuration register to store configuration information regarding the computer bus device;
• a second configuration register to store configuration information regarding the alternate computer bus device, wherein the alternate computer bus device is directly coupled to the host bus;
• a target interface directly coupled to the host bus, the target interface being structured to receive a configuration command from the processor, determine whether the configuration command includes configuration information regarding the computer bus device or the alternate computer bus device, cause the configuration information to be stored in the first configuration register if the configuration information is regarding the computer bus device, and cause the configuration information to be stored in the second configuration register if the configuration information is regarding the alternate computer bus device;
• and
• a bus bridge coupled between the computer bus device and a peripheral bus, the computer bus device being structured to forward a transaction request from the host bus to the bus bridge via the peripheral bus in response to determining that the transaction request is directed to other than the alternate computer bus device based on the configuration data stored in the second configuration register.

A computer system configured to process addressing data and transaction requests from a processor transmitted by the processor on a bus, comprising:

• a plurality of interconnection devices for interconnecting the bus with memory, additional buses, and peripherals, the plurality of interconnection devices, including a primary interconnection device and a plurality of secondary interconnection devices, connected to the bus in a peer arrangement without any interconnection devices hierarchically interconnected between the bus and the interconnection devices;
• the primary interconnection device further comprising at least one configuration register structured to store addressing data regarding configuration of the plurality of secondary interconnection devices, the primary interconnection device further comprising logic structured to ignore transaction requests directed to the plurality of secondary interconnection devices based on the addressing data stored;
• each of the plurality of secondary interconnection devices further comprising at least one configuration register structured to store addressing data regarding its own configuration, each of the second interconnection devices further comprising logic structured to ignore transaction requests directed to any of the other interconnection devices based on the addressing data stored and to communicate that each of the plurality of secondary interconnection devices is interconnected to the bus through the primary interconnection device in response to configuration read requests from the processor.