Processing circuit and a search processor circuit

A processing circuit (P1) for recognition and comparison of complex patterns in high-speed data streams, particularly for use in search engines for search and retrieval of data stored in structured or unstructured databases, and wherein the processing circuit (P1) forms a node in a network of such processing circuits, characterized in that the processing circuit (P1) comprises an interface with inputs and outputs for data which respectively are configuring and operational parameters for the processing circuit (P1), the configuring parameters being supplied to the processing circuit (P1) via unspecified or dedicated inputs in the interface once and for all for a giving processing task and the operational data which are processed by execution of the given processing task being continuously input to or output from the processing circuit (P1) via specified respective inputs and outputs of the interface, at least one kernel processor (P0) in the form of a comparator unit (COM), the comparator unit (COM) being adapted for comparing two data words, and a logic unit (E) connected with the comparator unit, the logic unit comprising a multiplexer (MUX1) connected with the following inputs in the interface:

• a sequential data input, a sequential document input, a sequential flip-fiop input, a sequential result input from a preceding processing circuit, a sequential result input from a succeeding processing circuit, a parallel data input, a parallel document input, a parallel flip-flop input, a parallel result input on a preceding processing circuit and a parallel result input on a succeeding processing circuit;
• and with the following outputs in the interface:
• an output for a selected data value, an output for a selected document value, an output for a selected flip-flop value, an output for a selected result to a preceding processing circuit and an output for selected document value, an output for selected flip-flop value, an output for a selected result to a preceding processing circuit, and an output for selected result to a succeeding processing circuit;
• a first D fip-flop (2);
• a latency unit (LAT) which is adapted to delay a positive binary value with a given number of time units;
• a second D flip-flop (4);
• a sequence control unit (SC) which is adapted to monitor and control a comparison operation in the comparator unit (COM), and a result selector which is adapted to combine two result values from other processing circuits or other result selectors;
• that the comparator unit (COM) is connected with an output for a selected data value on a multiplexer (MUX1) and with a data output in the interface and further has a result output connected with a first AND gate (1) and an equality unit connected with a second AND gate (3), that the first D flip-flop is connected with an output for a selected document value on the multiplexer (MUX1) and has a reset output which via a reset line (5) is connected respectively with an input on the first AND gate (1), an input on the second AND gate (3), and an input on the latency unit (LAT) as well as with a document input in the interface, that the second AND gate (3) has an equality output in the interface, that the latency unit (LAT) is connected with the output on the first AND gate (1) and with a result input on the sequence control unit (SC), that the second D flip-flop (4) is connected with the reset output on the first D flip-flop (2) and respectively a flip-flop output and flip-flop input on the sequence control unit (SC) as well as with a flip-flop output in the interface, that the sequence control unit (SC) is connected with the output for a selected flip-flop value and the output for a selected result from a preceding processing circuit on the multiplexer (MUX1) and with a result input on a preceding processing circuit and result output in the interface, and that the result selector (RS) is connected with respectively a first result input, a first document input, a first equality input, a second result input, a second document input, and a second equality input in the interface and respectively with a result output, a document output and an equality output in the interface.