System and method for delay line testing

A method of testing a digital delay line comprising successive delay stages collectively representing a time window, and wherein said successive delay stages divide said time window into corresponding successive time bins, said testing method comprising:

• generating a test signal that shifts through a plurality of time offsets at known time intervals relative to said beginning of time window;
• recording samples of said test signal at sample points fixed by said delay stages of said delay line;
• and
• determining whether said recorded samples of said test signal fall within said successive time bins as expected based on said known time intervals.

A circuit for generating a test signal that shifts in time relative to a reference signal at a known rate, the circuit comprising:

• first and second frequency generators to generate a first signal and said test signal, respectively;
• a differencing circuit to generate a frequency difference signal based on a difference frequency between said first signal and said test signal;
• a control circuit to lock said test signal a desired offset frequency away from a frequency of said first signal based on comparing said frequency difference signal to a difference control signal;
• and
• a first divider circuit to generate said reference signal by dividing said first signal, such that said test signal and said reference signal have a linearly changing phase offset and corresponding time shift based on said desired offset frequency.