Method and apparatus providing improved data path calibration for memory devices
AssigneeMicron Technology, Inc.
InventorsBrian Johnson, Brent Keeth
Life of this patent
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Abstract
A method and apparatus for calibrating a data path of a digital circuit uses an even bit pseudo-random calibration pattern. A portion of the pattern is captured in a capture period and used to predict a next arriving portion of the calibration pattern. The next arriving portion of the calibration pattern is captured and then compared to the predicted pattern in a compare period, and the result of the comparison is used to relatively time data arriving in the data path to a clocking signal which clocks in the data. The time duration of the compare period may be varied to ensure that all possible bits of the calibration pattern are used in the calibration procedure.
Claims16
A method of calibrating a data path of a digital device comprising:
- a) capturing a first predetermined number of bits of a repeating calibration pattern received on said data path during a first capture period corresponding to a first predetermined number of ticks of a clock signal;
- b) predicting a second predetermined number of bits of said repeating calibration pattern to be received on said data path from said first predetermined number of bits;
- c) capturing a third predetermined number of bits of said repeating calibration pattern during a second capture period corresponding to said first predetermined number of ticks of said clock signal;
- d) comparing said predicted second predetermined number of bits with said captured third predetermined number of bits during a compare period corresponding to a second number of ticks of said clock signal;
- e) using the results of said comparison to adjust the relative timing of said received calibration pattern and said clock signal;
- and
- f) repeating steps “a” through “e” a plurality of times wherein for at least a first number of said times said second number of ticks equals a first number of ticks and for at least a second number of times said second number of ticks does not equal said first number of ticks.
A method of calibrating a data path of a digital device, comprising:
- capturing a first predetermined number of bits of a repeating calibration pattern received on said data path during a first capture period corresponding to a first predetermined number of ticks of a clock signal;
- predicting a second predetermined number of bits of said repeating calibration pattern to be received on said data path from said first predetermined number of bits;
- capturing a third predetermined number of bits of said repeating calibration pattern during a second capture period corresponding to said first predetermined number of ticks of said clock signal;
- comparing said predicted second predetermined number of bits with said captured third predetermined number of bits during a compare period corresponding to a second number of ticks of said clock signal;
- and
- using the results of said comparison to adjust the relative timing of said received calibration pattern and said clock signal.
Dependencies are inferred from the claim text.