Reference timer for frequency measurement in a microprocessor

An apparatus comprising:

• circuitry to generate a first timing window and a second timing window, the circuitry including:
• a capacitor having a capacitor voltage;
• first multiplexer coupled to the counter to select between a first reference voltage and a second reference voltage and to output a first multiplexer reference voltage;
• and
• second multiplexer coupled to the first multiplexer to select between the first multiplexer reference voltage and a third reference voltage and to output a second multiplexer reference voltage;
• first switch coupled to the capacitor and the second multiplexer to close if the capacitor voltage is less than the second multiplexer reference voltage and to open if the capacitor voltage is greater than or equal to the second multiplexer reference voltage;
• and second switch coupled to the capacitor and the second multiplexer to close if the capacitor voltage is greater than or equal to the second multiplexer reference voltage and to open if the capacitor voltage is less than the second multiplexer reference voltage;
• a counter to count clock cycles during the first and second timing windows;
• and
• logic coupled to the circuitry and the counter to cancel timing window error.

A method, comprising:

• for a predetermined number of times, charging a capacitor to first voltage and discharging the capacitor to a second voltage to define a first timing window;
• counting a number of clock cycles that occur during the first timing window;
• for the predetermined number of times, charging the capacitor to a third voltage and discharging the capacitor to the second voltage to define a second timing window;
• counting a number of clock cycles that occur during the second timing window;
• subtracting the number of clock cycles counted during the second timing window from the number of clock cycles counted during the first timing window to generate a third number of clock cycles;
• and
• determining whether the clock signal's frequency exceeds a predetermined threshold frequency based on the third number of clock cycles.

A computer program product, comprising:

• first computer readable program code embodied in a computer usable medium to cause a computer to start a first timing window, to count clock cycles of a clock signal that occur during the first timing window, and to stop the first timing window;
• second computer readable program code embodied in a computer usable medium to cause the computer to start a second timing window, to count clock cycles of the clock signal that occur during the second timing window, and to stop the second timing window;
• third computer readable program code embodied in a computer usable medium to cause the computer to subtract the number of clock cycles counted during the second timing window from the number of clock cycles counted during the first timing window to generate difference;
• fourth computer readable program code embodied in a computer usable medium to cause the computer to cease operations if the difference is greater than a threshold corresponding to a preselected frequency threshold for the clock signal;
• and
• fifth computer readable program code embodied in a computer usable medium to cause the computer to provide a first reference voltage during the first timing window and a second reference voltage during the second timing window, and to cause the computer to compare a voltage level of the device to the first and second reference voltages during the first and second timing windows, respectively.