Subpicture master control
AssigneesSony Corporation, Sony Electronics Inc.
InventorsPattabiraman Subramanian, Ibrahim Cem Duruoz
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AssigneesSony Corporation, Sony Electronics Inc.
InventorsPattabiraman Subramanian, Ibrahim Cem Duruoz
Estimating the term…
A method for operating a digital video processor including a CPU and a memory to control the presentation of demultiplexed subpicture unit (“SPU”) data. The play back of the subpicture is synchronized with a system clock having a clock rate varying as a function of a desired play back speed selected by a user. The method first tests during a vertical blanking period, consecutive ones of the SPU's to identify a first SPU including a PTS value having a desired relationship with respect to a value of the system clock. Next, the video processor tests during the vertical blanking period, consecutive ones of the DCSQ commands in the first SPU to identify one or more DCSQ commands with a start time value having a desired relationship with respect to the value of the system clock. Thereafter, the one or more of the DCSQ commands associated with the first SPU are parsed, and subpicture data associated with one of the parsed DCSQ commands is displayed.
A method of operating a digital video processor including a CPU and a memory to control the presentation of demultiplexed subpicture data, the subpicture data comprising a serial stream of subpicture units (“SPU's”), each of the SPU's including in part a plurality of display control sequence (“DCSQ”) commands and associated start time values, a start of each of the SPU's being defined by a presentation time stamp (“PTS”) associated therewith, the play back of the subpicture being synchronized with a system clock having a clock rate varying as a function of a desired play back speed selected by a user, the method comprising:
A method of operating a digital video processor including a CPU and a memory to control the presentation of demultiplexed subpicture data, the subpicture data comprising a serial stream of subpicture units (“SPU's”), each of the SPU's including in part a plurality of display control sequence (“DCSQ”) commands and associated start times, a start of each of the SPU's being defined by a presentation time stamp (“PTS”) associated therewith, the play back of the subpicture being synchronized with a system clock having a clock rate varying as a function of a desired play back speed selected by a user, the method comprising:
A method of operating a digital video decoder including a CPU and memory to control the presentation of demultiplexed subpicture data, the subpicture data comprising a serial stream of subpicture units (“SPU's”), each of the SPU's including in part a plurality of display control sequence (“DCSQ”) commands and associated start times, a start of each of the SPU's being defined by a presentation time stamp (“PTS”) associated therewith, the play back of the subpicture being synchronized with a system time clock having a clock rate varying as a function of a desired play back speed selected by a user, the method comprising:
Dependencies are inferred from the claim text.