Method for attenuating transients caused by aligning in a desynchronizer
AssigneeNokia Corporation
InventorReino Urala
Life of this patent
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Abstract
The invention relates to a method to attenuate transients caused in the desynchroniser by justification events in a digital transmission system. The analogue circuit arrangement realizing the method comprises a by-pass input for receiving the three-state signal (BPin), whereby the signal (BPin) represents justification events upwards and/or downwards, filtering means (R8 and C8) for filtering the pulse signal (BPin), and adding means (AMP2) for adding the filtered pulse signal to the output signal of the loop filter (AMP1), whereby the added output signal controls the loop oscillator (VCO).
Claims9
A method to attenuate transients caused in a desynchroniser by stuffing events in a digital transmission system comprising a data buffer (1), a write address counter (2) controlled by a write clock (CLK1), a read counter (3) controlled by a read clock (CLK2), and a phase locked loop (PLLa;
- PLLd), which contains a phase discriminator (4, PD), a loop filter (AMP, AMP1;
- LOOP FILTER) and a controlled oscillator (5, VCO;
- DCO) for controlling the read and write clocks on the basis of a phase difference, said method comprising the steps of:
- forming a pulse signal (BPin) representing justification events upwards and/or downwards caused by phase changes in a tributary unit signal;
- directing the pulse signal (BPin) through second filtering means (R8 and C8;
- LPF);
- and
- adding the filtered pulse signal (AMP2;
- SUM) to the output signal of the loop filter (AMP1;
- LOOP FILTER), whereby the summed output signal controls the loop oscillator (VCO;
- DCO).
A circuit arrangement to attenuate transients caused in a desynchroniser by stuffing events in a digital transmission system comprising a data buffer (1), a write address counter (2) controlled by a write clock (CLK1), a read counter (3) controlled by a read clock (CLK2), and a phase locked loop (PLLa;
- PLLd), which contains a phase discriminator (4, PD), a loop filter (AMP, AMP1;
- LOOP FILTER) and a controlled oscillator (5, VCO;
- DCO) for controlling the read and write clocks on the basis of a phase difference, said circuit arrangement further comprising a by-pass input for receiving a pulse signal (BPin), whereby the pulse signal (BPin) represents justification events upwards and/or downwards, filtering means (R8 and C8;
- LPF) for filtering the pulse signal (BPin), and adding means (AMP2, SUM) for adding the filtered pulse signal to the output signal of the loop filter (AMP1;
- LOOP FILTER), whereby the added output signal controls the loop oscillator (VCO;
- VCO).
Dependencies are inferred from the claim text.