Clock recovery circuit and a receiver having a clock recovery circuit
AssigneeKoninklijke Philips Electronics N.V.
InventorsEric De Mey, Jonathan L. Watson, Brian G. Maloney
Life of this patent
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Abstract
A data receiver comprises a receiver for receiving a data signal and providing a base band output, a demodulator coupled to an output of the receiving means receiver for providing a data output, and a clock recovery circuit coupled to an output of the demodulator for recovering symbols represented by the data output. The clock recovery circuit is operable to determine a time difference between rising and falling edges in the data output and their nominal reference points, and to determine respective clock reference points for the rising and falling edges from the time difference between the rising and falling edges.
Claims15
A receiver, comprising:
- receiving means for receiving a data signal and providing a base band output;
- demodulating means coupled to an output of the receiving means for providing a data output;
- and
- symbol recovery means coupled to an output of the demodulating means for recovering symbols represented by the data output,
- wherein said symbol recovery means includes
- edge determination means for determining one or more occurrences of rising and falling edges in the data output,
- difference determination means for determining one or more differences between the one or more occurrences of rising and falling edges, and
- phase locked loop means for utilizing the one or more differences for determining a clock reference position.
A clock recovery circuit, comprising:
- edge determination means for determining one or more occurrences of rising and falling edges in a data signal,
- difference determination means for determining one or more differences between the one or more occurrences of rising and falling edges, and
- phase locked loop means for utilizing the differences for determining a clock reference position.
A method of recovering symbols in a data signal, comprising:
- determining one or more occurrences of rising and falling edges in the data signal,
- determining one or more differences between the one or more occurrences of rising and falling edges, and
- utilizing the differences for determining a clock reference position.
A receiver, comprising:
- a demodulator operable to provide a data signal;
- and
- a clock recovery circuit,
- wherein said clock recovery circuit is operable to determine one or more occurrences of rising and falling edges in the data signal,
- wherein said clock recovery circuit is further operable to determine one or more differences between the one or more occurrences of rising and failing edges, and
- wherein said clock recovery circuit is further operable to determine a clock reference position based upon the one or more differences between the one or more occurrences of rising and falling edges.
A receiver, comprising:
- receiving means for receiving a data signal and providing a base band output;
- demodulating means coupled to an output of the receiving means for providing a data output;
- and
- symbol recovery means coupled to an output of the demodulating means for recovering symbols represented by the data output,
- wherein said symbol recovery means includes
- rising and falling edge phase locked loop means for determining one or more occurrences of rising and falling edges in the data output, and
- phase locked loop means for determining a clock reference position from a minimum circular mean of phases in said rising and falling edge phase locked loop means.
A clock recovery circuit, comprising:
- rising and falling edge phase locked loop means for determining one or more occurrences of rising and falling edges in the data output, and
- phase locked loop means for determining a clock reference position from a minimum circular mean of phases in said rising and falling edge phase locked loop means.
A method of recovering symbols in a data signal, comprising:
- operating a pair of phased locked loops to determine one or more occurrences of rising and falling edges in the data signal;
- and
- determining a clock reference position from a minimum circular mean of phases in the pair of phase locked loops.
Dependencies are inferred from the claim text.