Phase detector architecture for phase error estimating and zero phase restarting

A system incorporating a phase detector having an input and an output, a timing recovery circuit, and in association with a memory, comprising:

• a native timing gradient circuit and a non-native timing gradient circuit, for
• generating first and second outputs TG0 and TG1, respectively;
• and
• a comparator for receiving said TG0 and TG1 and comparing values thereof,
• wherein, if said native timing gradient circuit has a timing instance closer to zero phase error than said non-native timing gradient circuit, then an adjustment value, x, a number associated with said native timing gradient circuit, is inputted to the timing recovery circuit, and
• wherein, if said non-native timing gradient circuit has a timing instance closer to zero phase error than said native timing gradient circuit, then an equivalent of 180° is added to said adjustment value x.

A phase detector, having an input and an output, and an association with a memory and a timing recovery circuit, comprising:

• a native timing gradient circuit and a non-native timing gradient circuit, for generating first and second outputs TG0 and TG1, respectively;
• and
• a comparator for receiving said TG0 and TG1 and comparing values thereof,
• wherein, if said native timing gradient circuit has a timing instance closer to zero phase error than said non-native timing gradient circuits, then an adjustment value, x, a number associated with said native timing gradient circuit, is inputted to the timing recovery circuit, and
• wherein, if said non-native timing gradient circuit has a timing instance closer to zero phase error than said native timing gradient circuit, then an equivalent of 180° is added to said adjustment value x.

A mass data storage system incorporating a phase detector having an input and an output, and an association with a memory and a timing recovery circuit, comprising:

• a native timing gradient circuit and a non-native timing gradient circuit, for generating first and second outputs TG0 and TG1, respectively;
• and
• a comparator for receiving said TG0 and TG1 and comparing values thereof,
• wherein, if said native timing gradient circuit has a timing instance closer to zero phase error than said non-native timing gradient circuits, then an adjustment value, x, a number associated with said native timing gradient circuit, is inputted to the timing recovery circuit, and
• wherein, if said non-native timing gradient circuit has a timing instance closer to zero phase error than said native timing gradient circuit, then an equivalent of 180° is added to said adjustment value x.