Efficient apparatus and method for generating a trellis code from a shared state counter

An apparatus for decoding a stream of binary digits encoded according to a convolutional code, said apparatus comprising:

• a bus;
• a N-bit counter coupled to said bus, said N-bit counter adapted to generate a sequence of N binary bits;
• and
• a trellis code generator coupled to said N-bit counter, said trellis code generator comprising a first logical gate and a second logical gate;
• said trellis code generator adapted to specify a first set of binary digit from said sequence of N binary bits and to pass said first set of binary digits through said first logical gate to produce a first binary value, wherein said first set of binary digits is specified so that said first binary value emulates a first value of a first encoded bit determined using said convolutional code;
• said trellis code generator further adapted to specify a second set of binary digits from said sequence of N bits and to pass said second set of binary digits through said second logical gate to produce a second binary value, wherein said second set of binary digits is specified so that said second binary value emulates a first value of a second encoded bit determined using said convolutional code.

In a receiver used in a communication system, an apparatus for decoding a stream of binary bits encoded according to a convolutional code, said apparatus comprising:

• a bus;
• a N-bit counter coupled to said bus, said N-bit counter adapted to generate a sequence of N binary bits;
• a trellis code generator coupled to said N-bit counter;
• and
• a Viterbi decoder coupled to said N-bit counter, said Viterbi decoder adapted to compute metrics for encoded bits received by said receiver and to perform a traceback operation;
• said Viterbi decoder further comprising:
• a first memory register for storing said metrics, wherein an address in said first memory register is generated using said sequence of N binary digits;
• and
• a second memory register for storing information for said traceback operation, wherein an address in said second memory register is generated using said sequence of N binary digits.