Time slot assignment circuit

A time slot assignment circuit comprising:

• an input port which receives as input upper side incoming transmission data from a first ring network side of first data transmission rate and lower side incoming transmission data from a second ring network side of second data transmission rate, wherein the first data transmission rate is greater than the second data transmission rate;
• an output port from which the upper side outgoing transmission data is output to the first ring network side and the lower side outgoing transmission data is output to the second ring network side;
• and
• a time slot assignment function block which has a time switch and a space switch and supplies said upper side and lower side outgoing transmission data, obtained by interchanging channels for said upper side and lower side incoming transmission data from said input port to said output port, wherein said interchanging is performed by processing, in bit units, on N bits forming each of said channels, from the most significant bit to the least significant bit, for the respective bits individually, wherein
• said input port receives an input said upper side incoming transmission data and said lower side incoming transmission data as a predetermined number of multiplex level data groups each including a plurality of channels of the same multiplex level-formatted N-bit configuration, where N is a positive whole number;
• said upper side outgoing transmission data and said lower side outgoing transmission data are output from said output port as the above predetermined number of multiplex level data groups each comprised of a plurality of channels of the same multiplex level-formatted N-bit configuration;
• and
• said time slot assignment function block is comprised of N time slot assignment function modules having the same configuration as each other and the N number of time slot assignment function modules are alloted so as to perform processing, in bit units, on the N bits forming each channel of the multiplex level data group, from the most significant bit to the least significant bit.